Charge pump switch circuits

• US 5,537,072 A
• Filed: 06/30/1994
• Issued: 07/16/1996
• Est. Priority Date: 06/30/1994
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Canclini, Athos
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): KIM, JUNG H
• Application Number:
  US08/268,850
• Time in Patent Office: 747 Days
• Field of Search: 327/103, 327/108, 327/374, 327/404, 327/421, 327/437, 327/584, 327/111, 327/264, 327/377
• US Class Current: 327/374
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

A switch circuit for a charge pump circuit is disclosed. The switch circuit has a first transistor for conducting current and is controlled by a second, third, and fourth transistor. The second transistor protects the first transistor for excessive gate-to-drain voltage. The third transistor receives the signal for switching the switch circuit and also serves as a cascoding transistor for protecting the fourth transistor from excessive gate-to-drain voltage. Consequently, the switch circuit can withstand high gate-to-drain voltages and has increased reliability. The switch also has a turn-off circuit to facilitate the depletion of charge on the control element of the first transistor. The switch circuit also has a zener diode to insure that excessive voltage is not applied across the gate-to drain of the first transistor.

Claims

1. A circuit for switching a current on and off comprising:

a first transistor having a control element and having a current path with an input voltage side and an output voltage side;

a second transistor having a control element and having a current path with a first end and a second end, the first end of said second transistor being connected to the input voltage side of said first transistor, the control element and the second end of said second transistor being connected to the control element of said first transistor;

a third transistor having a control element for receiving a timing control signal, and having a current path with a first end and a second end, the first end of said third transistor being connected to the second end of said second transistor;

a fourth transistor having a control element for receiving a first bias voltage and having a current path with a first end and a second end, the first end of said fourth transistor being connected to the second end of said third transistor and the second end of said fourth transistor being connected to a voltage reference;

a fifth transistor having a current path having a first end and a second end, the first end of said fifth transistor being connected to the input side of the current path of said first transistor and the second end of said fifth transistor being connected to the control element of said first transistor;

a sixth transistor having a control element connected to the control element of said fifth transistor and having a current path with a first end and a second end, the first end of said sixth transistor being connected to said first end of said fifth transistor;

a seventh transistor having a control element and having a current path with a first end and a second end, the first end of said seventh transistor being connected to the second end of said sixth transistor and the control element of said sixth transistor;

an inverter having an input connected to the control element of said third transistor and having an output connected to the control element of said seventh transistor; and

an eighth transistor having a control element for receiving a second bias voltage and having a current path with a first end connected to the second end of said seventh transistor and a second end connected to the voltage reference.

2. The circuit of claim 1 wherein said first transistor comprises a p-channel field effect transistor.

3. The circuit of claim 1 wherein said second transistor comprises a p-channel field effect transistor.

4. The circuit of claim 1 wherein said third transistor and fourth transistor comprise n-channel field effect transistors.

5. The circuit of the claim 1 further comprising a zener diode having an anode connected to the control element of said first transistor and having a cathode connected to the output voltage side of said first transistor, for protecting said first transistor from excessive voltage.

6. The circuit of claim 1 wherein said fifth transistor comprises a p-channel field effect transistor and said sixth transistor comprises a p-channel field effect transistor.

7. A circuit for switching a current on and off comprising:

a first transistor having a source, having a drain, and having a control element, wherein the source and the drain form a conduction path of said circuit;

a second transistor having a source connected to the source of said first transistor, having a drain, and having a gate connected to the gate of said first transistor and to the drain of said second transistor;

a third transistor having a drain connected to the drain of said second transistor, having a source, and having a gate for receiving a timing control signal;

a fourth transistor having a drain connected to the source of said third transistor, having a source connected to a voltage reference, and having a gate for receiving a first bias voltage;

a zener diode having an anode connected to the gate of said first transistor and having a cathode connected to the source of said first transistor;

a fifth transistor having a source connected to the source of said first transistor, having a drain connected to the gate of said first transistor, and having a gate;

a sixth transistor having source connected to the source of said fifth transistor, having a drain connected its gate;

a seventh transistor having a drain connected to the drain of said sixth transistor, having a gate, and having a source;

an inverter having an input connected to the gate of said third transistor, and having an inverted output connected to the gate of said seventh transistor; and

an eighth transistor having a gate for receiving a second bias voltage, having a drain connected to the source of said seventh transistor, and having a source connected to the voltage reference.

8. The circuit of claim 7 wherein said first transistor comprises a p-channel field effect transistor.

9. The circuit of claim 7 wherein said second transistor comprises a p-channel field effect transistor.

10. The circuit of claim 7 wherein said fifth transistor comprises a p-channel field effect transistor and said sixth transistor comprises a p-channel field effect transistor.

11. A charge pump circuit having a plurality of inverters, a plurality of capacitors, and a plurality of switches, wherein each of the plurality of switches comprise:

a first transistor having a source connected to an input node, having a drain connected to an output node, and having a control element, for selectively conducting current from said input node to said output node;

a second transistor having a source connected to the source of said first transistor, having a drain, and having a gate connected to the gate of said first transistor and to the drain of said second transistor, for facilitating a turn-off of said first transistor;

a third transistor having a drain connected to the drain of said second transistor, having a source, and having a gate for receiving a timing control signal;

a fourth transistor having a drain connected to the source of said third transistor, having a source connected to a reference voltage, and having a gate for receiving a first bias voltage, so that said switching circuit withstands a high voltage from the source of said first transistor to the gate of said third transistor; and

a zener diode having an anode connected to the gate of said first transistor and having a cathode connected to the source of said first transistor;

a fifth transistor having a source connected to the source of said first transistor, having a drain connected to the gate of said first transistor, and having a gate;

a sixth transistor having source connected to the source of said fifth transistor, having a drain, and having a gate connected its drain and to the gate of said fifth transistor;

a seventh transistor having a drain connected to the drain of said sixth transistor, having a gate, and having a source;

an inverter having an input connected to the gate of said third transistor, and having an inverted output connected to the gate of said seventh transistor; and

an eighth transistor having a gate for receiving a second bias voltage, having a drain connected to the source of said seventh transistor, and having a source connected to a voltage reference.

12. The circuit of claim 11 wherein said first transistor comprises a p-channel field effect transistor.

13. The circuit of claim 11 wherein said second transistor comprises a p-channel field effect transistor.

14. The circuit of claim 11 wherein said fifth transistor comprises a p-channel field effect transistor and said sixth transistor comprises a p-channel field effect transistor.