Dynamic memory system having memory refresh

• US 5,537,565 A
• Filed: 12/27/1989
• Issued: 07/16/1996
• Est. Priority Date: 11/24/1969
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/457,451
• Time in Patent Office: 2,393 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/250, 395/400, 395/425, 395/550, 395/800, 365/73, 365/74, 365/75, 365/76, 365/77, 365/78, 365/79, 365/80, 365/189.01, 365/189.12, 365/222, 365/230.01, 365/238.5
• US Class Current: 711/105
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/12 : using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry. An improved memory architecture is provided that is particularly suitable for dynamic memories and integrated circuit data processors.

Claims

1. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a memory refresh circuit coupled to the dynamic memory the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips;

a memory address circuit generating a memory address;

a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals;

a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive a memory address from the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the selected at least one of the dynamic integrated circuit memory chips in response to the received memory address; and

a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal that is selectively coupled to each of the plurality of dynamic integrated circuit memory chips.

2. A dynamic memory system as set forth in claim 1, wherein the dynamic memory system further comprises:

a first clock circuit generating a first clock signal, wherein the memory address circuit is coupled to the first clock circuit and is adapted to generate the memory address in response to the first clock signal;

a second clock circuit generating a second clock signal; and

a second accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the memory accessing circuit.

3. A dynamic memory system as set forth in claim 2, wherein the second access circuit is further coupled to the memory address circuit and further operates in response to the memory address to access one of the plurality of digital data bits accessed from the dynamic memory by the first access circuit.

4. A dynamic memory system as set forth in claim 1,

wherein dynamic integrated circuit memory chips are dynamic integrated circuit shift register memory chips storing data bits in serial shift register form;

wherein the memory address circuit includes a data register circuit and a logic circuit the memory address circuit generating the memory address and

wherein the chip select circuit is coupled to the plurality of dynamic integrated circuit shift register memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit shift register memory chips in response to the memory chip select signals;

wherein the memory accessing circuit is coupled to the plurality of dynamic integrated circuit shift register memory chips and to the memory address circuit, the memory accessing circuit read accessing a plurality of data bits stored by at least one of the dynamic integrated circuit memory chips in response to the memory address; and

wherein the plurality of memory output circuits are coupled to the plurality of dynamic integrated circuit shift register memory chips and to the decoder circuit, the memory output circuits outputting at least one of the plurality of data bits read accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit shift register memory chips onto a memory output signal line that is common to the plurality of dynamic integrated circuit shift register memory chips.

5. A dynamic memory system as set forth in claim 1, wherein each of the plurality of dynamic integrated circuit memory chips includes a dynamic integrated circuit random access memory chip.

6. A dynamic memory system as set forth in claim 1,

wherein the dynamic memory system further comprises a first clock circuit generating a first clock signal and a second clock circuit generating a second clock signal;

wherein the memory address circuit is coupled to receive the first clock signal and is adapted to generate the memory address in response to the first clock signal;

wherein the dynamic memory system further comprises a second accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the memory accessing circuit;

wherein the memory accessing circuit includes a first address decoder circuit coupled to the memory address circuit, the first address decoder circuit generating first decoded signals in response to a first part of the memory address, and including a third accessing circuit coupled to the dynamic memory and to the first address decoder circuit, the third accessing circuit accessing the plurality of data bits from the dynamic memory in response to the first decoded signals; and

wherein the dynamic memory system further comprises;

a second address decoder circuit coupled to the memory address circuit, the second address decoder circuit generating second decoded signals in response to a second part of the memory address;

a fourth accessing circuit coupled to the memory accessing circuit, to the second clock circuit, and to the second address decoder circuit, the fourth accessing circuit operating in response to the second clock signal and the second decoded signals to access one of the plurality of data bits accessed by the memory accessing circuit; and

an output circuit coupled to the second accessing circuit, the output circuit outputting the accessed one of the plurality of data bits.

7. A dynamic memory system as set forth in claim 1, wherein the dynamic memory system further comprises:

a first clock circuit generating a first clock signal, wherein the memory address circuit is coupled to the first clock circuit and is adapted to generate the memory address in response to the first clock signal;

a second clock circuit generating a second clock signal; and

a second accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the memory accessing circuit; and

wherein the memory refresh circuit includes a refresh address counter circuit generating a refresh address and an address refresh circuit coupled to receive the refresh address from the refresh address counter circuit, the address refresh circuit refreshing the data bits stored by the dynamic memory in response to the received refresh address.

8. A dynamic memory system as set forth in claim 1,

wherein the dynamic memory system further comprises a first clock circuit generating a first clock signal and a second clock circuit generating a second clock signal;

wherein the memory address circuit is coupled to the first clock circuit and is adapted to generate the memory address in response to the first clock signal;

wherein the dynamic memory system further comprises a second accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the memory accessing circuit;

wherein the data bits include instruction data bits and operand data bits;

wherein the dynamic memory system further comprises a stored program computer coupled to the second accessing circuit, the stored program computer processing an operand data bit accessed by the second accessing circuit in response to an instruction data bit accessed by the second accessing circuit; and

wherein the memory refresh circuit includes a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory, the synchronized refresh circuit refreshing the data bits stored by the dynamic memory in synchronization with the processing of the data bit by the stored program computer.

9. A dynamic memory system as set forth in claim 1,

wherein the dynamic memory includes a plurality of pages of dynamic memory, each page having at least one of the plurality of dynamic integrated circuit memory chips;

wherein the dynamic memory system further comprises paging logic generating a page select signal to select one of the plurality of pages of dynamic memory; and

wherein the chip select circuit is further coupled to the paging logic and further operates in response to the page select signal to select the at least one but not all of the plurality of dynamic integrated circuit memory chips from the selected page of dynamic memory.

10. A dynamic memory system as set forth in claim 1, wherein the plurality of dynamic integrated circuit memory chips are partitioned into a main memory having at least one of the dynamic integrated circuit memory chips storing instruction data bits and operand data bits and a scratch pad memory having at least one of the dynamic integrated circuit memory chips and further comprising a stored program computer coupled to the memory accessing circuit, the stored program computer processing an operand data bit output by the plurality of memory output circuits in response to an instruction data bit output by the plurality of memory output circuits.

12. A dynamic memory system as set forth in claim 5 wherein the first access circuit includes a first address decoder circuit coupled to the memory address circuit and generating first decoded signals in response to a first part of the memory address and includes a third access circuit coupled to the dynamic memory and to the first address decoder circuit and accessing the plurality of digital data bits from the dynamic memory in response to the first clock signal;

wherein the second access circuit includes a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address and includes a fourth access circuit coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit, the fourth access circuit operating in response to the second clock signal and the second decoded signals to access one of the plurality of digital data bits accessed by the first access circuit; and

wherein the dynamic memory system further comprises an output circuit coupled to the second access circuit and outputting the accessed one of the plurality of digital data bits.

11. A dynamic memory system comprising:

a dynamic memory for storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit coupled to the first clock circuit generating a memory address in response to the first clock signal;

a first access circuit coupled to the dynamic memory and to the memory address circuit and read accessing a plurality of digital data bits in the dynamic memory in response to the memory address;

a second access circuit coupled to the first access circuit and to the second clock circuit, the second access circuit operating in response to the second clock signal to read access one of the plurality of digital data bits read accessed in the dynamic memory by the first access circuit; and

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.

13. A dynamic memory system as set forth in claim 11, wherein the dynamic memory includes a plurality of pages of dynamic shift registers storing the digital data bits;

wherein the second clock circuit includes an 8 MHz clock circuit generating the second clock signal as an 8 MHz clock signal having the second clock period as an 8 MHz clock period that is shorter than the first clock period of the first clock signal;

wherein the memory address circuit includes a decoder circuit generating the memory address in response to the first clock signal;

wherein the dynamic memory system further comprises paging logic coupled to the plurality of pages of dynamic shift registers and selecting one of the plurality of pages of dynamic shift registers;

wherein the first access circuit is further coupled to the paging logic and operates in response to the memory address to read access the plurality of digital data bits in the page of dynamic shift registers;

wherein the first access circuit is further coupled to the paging logic and operates in response to the memory address to read access the plurality of digital data bits in the page of dynamic shift registers selected the by paging logic;

wherein the first access circuit includes a gating circuit read accessing the plurality of digital data bits in the dynamic shift registers in response to the first clock signal and in response to the memory address;

wherein the second access circuit includes a selection circuit operating in response to the 8 MHz clock signal to read access one of the plurality of digital data bits read accessed in the dynamic memory by the first access circuit;

wherein the digital data bits include instruction digital data bits and operand digital data bits;

wherein the dynamic memory system further comprises a stored program computer coupled to the second access circuit and processing an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit;

wherein the memory refresh circuit includes a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory and refreshing the digital data bits stored by the dynamic memory in synchronization with the processing of the digital data bit by the stored program computer; and

wherein the dynamic memory system further comprises a refreshable character display coupled to the dynamic memory and displaying numeric characters in response to the digital data bits stored by the dynamic memory.

14. A dynamic memory system as set forth in claim 11, wherein the dynamic memory includes a plurality of dynamic shift registers storing the digital data bits;

wherein the first clock circuit includes a data address register clock circuit generating the first clock signal as a data address register clock signal having the first clock period as a data address register clock period;

wherein the second clock circuit includes an 8 MHz block circuit generating the second clock signal as an 8 MHz clock signal having the second clock period as an 8 MHz clock period that is shorter than the D register clock period of the data address register clock signal;

wherein the memory address circuit includes a data address register circuit generating the memory address in response to the data address register clock signal;

wherein the first access circuit includes a decoder circuit accessing the plurality of digital data bits from the dynamic shift registers in response to the data address register clock signal; and

wherein the second access circuit includes a selection circuit operating in response to the 8 MHz clock signal to write access one of the plurality of digital data bits write accessed in the dynamic shift registers by the first access circuit;

wherein the digital data bits include instruction digital data bits and operand digital data bits;

wherein the dynamic memory system further comprises a stored program computer coupled to the second access circuit and processing an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit;

wherein the memory refresh circuit includes a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory and refreshing the digital data bits stored by the dynamic memory in synchronization with the processing of the digital data bit by the stored program computer; and

wherein the dynamic memory system further comprises a refreshable character display coupled to the dynamic memory and displaying numeric characters in response to the digital data bits stored by the dynamic memory.

15. A dynamic memory system as set forth in claim 11, wherein the dynamic memory includes a plurality of dynamic integrated circuit memory chips each dynamic integrated circuit memory chip storing digital data bits;

wherein the first access circuit includes a first address decoder circuit coupled to the memory address circuit and generating first decoded signals in response to a first part of the memory address and includes a third access circuit coupled to the dynamic memory and to the first address decoder circuit and write accessing a plurality of digital data bits in each of the dynamic integrated circuit memory chips in response to the first clock signal;

wherein the second access circuit includes a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address and includes a fourth access circuit coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit and operating in response to the second clock signal and the second decoded signals to write access one of the plurality of digital data bits read accessed by the first access circuit;

wherein the dynamic memory system further comprises a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the first address decoder circuit and selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the first decoded signals; and

wherein the dynamic memory system further comprises a plurality of memory output circuits coupled to the first access circuit and to the second access circuit and outputting the accessed one of the plurality of digital data bits write accessed by the second access circuit in a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line common to the plurality of dynamic integrated circuit memory chips in response to the first decoded signals;

wherein the digital data bits include instruction digital data bits and operand digital data bits;

wherein the dynamic memory system further comprises a stored program computer coupled to the second access circuit and processing an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit;

wherein the memory refresh circuit includes a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory and refreshing the digital data bits stored by the dynamic memory in synchronization with the processing of the digital data bit by the stored program computer; and

wherein the dynamic memory system further comprises a refreshable character display coupled to the dynamic memory and displaying numeric characters in response to the digital data bits stored by the dynamic memory.

16. A dynamic memory system as set forth in claim 11, wherein the dynamic memory includes a dynamic random access memory storing the digital data bits;

wherein the second clock circuit includes an 8 MHz clock circuit generating the second clock signal as an 8 MHz clock signal having as the second clock period an 8 MHz clock period that is shorter than the first clock period of the first clock signal;

wherein the memory address circuit includes a decoder circuit generating the memory address in response to the first clock signal;

wherein the first access circuit includes a gating circuit accessing the plurality of digital data bits from the dynamic random access memory in response to the first clock signal and in response to the memory address; and

wherein the second access circuit includes a selection circuit operating in response to the 8 MHz clock signal to access one of the plurality of digital data bits accessed from the dynamic random access memory by the first access circuit.

17. A dynamic memory system as set forth in claim 11, wherein the second access circuit is further coupled to the memory address circuit and further operates in response to the memory address to access one of the plurality of digital data bits accessed from the dynamic memory by the first access circuit.

18. A dynamic memory system comprising:

a dynamic memory storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period, said second clock period being shorter than the first clock period of the first clock signal;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first access circuit coupled to the dynamic memory and to the memory address circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed by the first access circuit; and

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by dynamic memory.

19. A dynamic memory system as set forth in claim 18, wherein the first access circuit further includes a first address decoder circuit coupled to the memory address circuit, the first access circuit generating first decoded signals in response to a first part of the memory address, and a third access circuit that is coupled to the dynamic memory and to the first address decoder circuit and write accesses the plurality of digital data bits in the dynamic memory in response to the first decoded signals;

wherein the second access circuit further includes a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address, and includes a fourth access circuit that is coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit and operates in response to the second clock signal and the second decoded signals to access one of the plurality of digital data bits accessed by the first access circuit; and

wherein the dynamic memory system further comprises an output circuit that is coupled to the second access circuit and outputs the accessed one of the plurality of digital data bits.

20. A dynamic memory system as set forth in claim 18, wherein the digital data bits include instruction digital data bits and operand digital data bits, wherein the dynamic memory system further comprises a stored program computer that is coupled to the second access circuit and processes an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit, and wherein the memory refresh circuit includes a synchronized refresh circuit that is coupled to the stored program computer and to the dynamic memory and refreshes the digital data bits stored by the dynamic memory in synchronization with the processing of the digital data bit by the stored program computer.

21. A dynamic memory system as set forth in claim 18,

wherein the dynamic memory includes a plurality of pages of dynamic memory;

wherein the dynamic memory system further comprises paging logic generating a page select signal to select one of the plurality of pages of dynamic memory; and

wherein the first access circuit is further coupled to the paging logic and further operates in response to the page select signal to write access the plurality of digital data bits in the page of dynamic memory that is selected by the paging logic.

22. A dynamic memory system as set forth in claim 18, wherein the dynamic memory includes a dynamic main memory storing instruction digital data bits and operand digital data bits and a dynamic scratch pad memory storing operand digital data bits and wherein the dynamic memory system further comprises a stored program computer that is coupled to the second access circuit and processes an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit.

23. A dynamic memory system as set forth in claim 18, wherein the second access circuit is further coupled to the memory address circuit and further operates in response to the memory address to access one of the plurality of digital data bits accessed from the dynamic memory by the first access circuit.

24. A dynamic memory system comprising:

a dynamic memory for storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period that is shorter than the first clock period of the first clock signal;

a memory address circuit that is coupled to the first clock circuit and generates a memory address in response to the first clock signal;

a first access circuit that is coupled to the dynamic memory and to the memory address circuit and accesses a plurality of digital data bits in the dynamic memory in response to the memory address;

a second access circuit that is coupled to the first access circuit and to the second clock circuit and operates in response to the second clock signal to access in sequence at least two of the plurality of digital data bits accessed by the first access circuit; and

a memory refresh circuit that is coupled to the dynamic memory and refreshes the digital data bits stored by the dynamic memory.

25. A dynamic memory system as set forth in claim 24, wherein the first access circuit includes a first address decoder circuit that is coupled to the memory address circuit, that generates first decoded signals in response to a first part of the memory address, and that includes a third access circuit coupled to the dynamic memory and to the first address decoder circuit that write accesses the plurality of digital data bits from the dynamic memory in response to the first decoded signals;

wherein the second access circuit includes a second address decoder circuit that is coupled to the memory address circuit, that generates second decoded signals in response to a second part of the memory address and that includes a fourth access circuit coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit, the second access circuit operating in response to the second clock signal and the second decoded signals to write access one of the plurality of digital data bits accessed by the first access circuit; and

wherein the dynamic memory system further comprises an output circuit that is coupled to the second access circuit and outputs the accessed one of the plurality of digital data bits.

26. A dynamic memory system as set forth in claim 24, wherein the second access circuit includes a multiple digital data bit access circuit that is coupled to the first access circuit and write accesses a plurality of the digital data bits accessed in the dynamic memory by the first access circuit in response to the second clock signal and wherein the dynamic memory system further comprises an output shifting circuit that is coupled to the second access circuit and outputs a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit.

27. A dynamic memory system as set forth in claim 24, wherein the second access circuit includes a multiple digital data bit access circuit coupled to the first access circuit and write accessing a plurality of the digital data bits accessed in the dynamic memory by the first access circuit in response to the second clock signal and wherein the dynamic memory system further comprises an output shifting circuit that is coupled to the second access circuit and outputs a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit and a display monitor displaying data in response to the plurality of digital data bits output by the output shifting circuit.

28. A dynamic memory system as set forth in claim 24, wherein the memory refresh circuit includes:

a refresh address counter generating a refresh address; and

the memory refresh circuit being coupled to the refresh address counter and refreshing the digital data bits stored by the dynamic memory in response to the refresh address.

29. A dynamic memory system as set forth in claim 24, wherein the digital data bits include instruction digital data bits and operand digital data bits, wherein the dynamic memory system further comprises a stored program computer coupled to the second access circuit and processing operand digital data bits accessed by the second access circuit in response to instruction digital data bits accessed by the second access circuit, and wherein the memory refresh circuit includes a synchronized refresh circuit that is coupled to the stored program computer and to the dynamic memory and refreshes the digital data bits stored by the dynamic memory in synchronization with the processing of the digital data bit by the stored program computer.

30. A dynamic memory system as set forth in claim 24, wherein the second access circuit is further coupled to the memory address circuit and further operates in response to the memory address to access one of the plurality of digital data bits accessed from the dynamic memory by the first access circuit.

31. A dynamic memory system comprising:

a dynamic memory for storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first address decoder circuit coupled to the memory address circuit and generating first decoded signals in response to a first part of the memory address;

a first access circuit coupled to the dynamic memory and to the first address decoder circuit and accessing a plurality of digital data bits from the dynamic memory in response to the first decoded signals;

a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address;

a second access circuit coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit and operating in response to the second clock signal and the second decoded signals to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit;

an output circuit coupled to the second access circuit and outputting the accessed one of the plurality of digital data bits; and

a memory refresh circuit coupled to the dynamic memory and refreshing the digital bits stored by the dynamic memory.

32. A dynamic memory system as set forth in claim 31, wherein the second access circuit includes a multiple digital data bit write access circuit that is coupled to the first access circuit and accesses a plurality of the digital data bits accessed in the dynamic memory by the first access circuit in response to the second clock signal and wherein the dynamic memory system further comprises an output shifting circuit coupled to the second access circuit that outputs a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit and a display monitor displaying data in response to the plurality of digital data bits output by the output shifting circuit.

33. A dynamic memory system as set forth in claim 31, wherein the memory refresh circuit includes:

a refresh address counter generating a refresh address; and

wherein the memory refresh circuit is coupled to the refresh address counter and refreshes the digital data bits stored by the dynamic memory in response to the refresh address.

34. A dynamic memory system as set forth in claim 31 wherein the digital data bits include instruction digital data bits and operand digital data bits, wherein the dynamic memory system further comprises a stored program computer that is coupled to the second access circuit and processes an operand digital data bit read accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit, and wherein the memory refresh circuit includes a synchronized refresh circuit that is coupled to the stored program computer and to the dynamic memory and refreshes the digital data bits stored by the dynamic memory in synchronization with the processing of the digital data bit by the stored program computer.

35. A dynamic memory system as set forth in claim 31, wherein the dynamic memory includes a dynamic main memory for storing instruction digital data bits and operand digital data bits, and a dynamic scratch pad memory for storing operand digital data bits and wherein the dynamic memory system further comprises a stored program computer coupled to the second access circuit, the stored program computer processing an operand digital data bit read accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit.

36. A dynamic memory system comprising:

a dynamic memory adapted to store digital data bits;

a first memory address circuit generating a first memory address;

a first address decoder circuit coupled to the first memory address circuit, the first address decoder circuit generating first decoded signals in response to the first memory address;

a first access circuit coupled to the first address decoder circuit and to the dynamic memory, the first access circuit accessing a plurality of digital data bits stored by the dynamic memory in response to the first decoded signals;

a second memory address circuit generating a second memory address;

a second address decoder circuit coupled to receive the second memory, address from the second memory address circuit, the second address decoder circuit generating second decoded address signals in response to the second memory address;

a second access circuit coupled to the first access circuit and coupled to receive the second decoded address signals from the second address decoder circuit, the second access circuit operating in response to the second decoded address signals to select one of the plurality of digital data bits accessed by the first access circuit;

an output circuit coupled to receive the selected digital data bit from the second access circuit, the output circuit outputting the selected digital data bit; and

a refresh circuit coupled to the dynamic memory, the refresh circuit refreshing the digital data bits stored by the dynamic memory.

37. A dynamic memory system as set forth in claim 36,

wherein the second access circuit includes a multiple digital data bit write access circuit coupled to the first access circuit, the multiple digital data bit write access circuit accessing a plurality of the digital data bits write accessed in the dynamic memory by the first access circuit in response to the second clock signal;

and

wherein the dynamic memory system further comprises;

an output shifting circuit coupled to the second access circuit, the output shifting circuit outputting a sequence of the plurality of digital data bits write accessed by the multiple digital data bit access circuit; and

a display monitor displaying data in response to the plurality of digital data bits output by the output shifting circuit.

38. A dynamic memory system as set forth in claim 36,

wherein the digital data bits include instruction digital data bits and operand digital data bits,

wherein the dynamic memory system further comprises a stored program computer coupled to the second access circuit, the stored program computer processing an operand digital data bit selected by the second access circuit in response to an instruction digital data bit selected by the second access circuit;

and

wherein the refresh circuit includes a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory, the synchronized refresh circuit refreshing the digital data bits stored by the dynamic memory in synchronization with the processing of the digital data bit by the stored program computer.

39. A dynamic memory system as set forth in claim 36,

wherein the dynamic memory includes a plurality of pages of dynamic memory;

wherein the dynamic memory system further comprises paging logic generating a page select signal to select one of the plurality of pages of dynamic memory; and

wherein the first access circuit is further coupled to the paging logic and further operates in response to the page select signal to read access the plurality of digital data bits from the page of dynamic memory selected by the paging logic.

40. A dynamic memory system as set forth in claim 36,

wherein the dynamic memory includes a dynamic main memory storing instruction digital data bits and operand digital data bits and a dynamic scratch pad memory storing operand digital data bits;

and wherein the dynamic memory system further comprises a stored program computer coupled to the second access circuit, the stored program computer processing an operand digital data bit selected by the second access circuit in response to an instruction digital data bit selected by the second access circuit.

41. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips;

a memory address circuit generating a memory address;

a decoder circuit coupled to receive a memory address from the memory address circuit and generating memory chip select signals in response to the received memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals;

a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by at least one of the dynamic integrated circuit memory chips in response to the memory address; and

a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line that is common to the plurality of dynamic integrated circuit memory chips.

42. A dynamic memory system as set forth in claim 41,

wherein the dynamic memory system further comprises a first clock circuit generating a first clock signal and a second clock circuit generating a second clock signal;

wherein the memory address circuit is coupled to the first clock circuit and is adapted to generate the memory address in response to the first clock signal;

wherein the dynamic memory system further comprises a second accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the memory accessing circuit;

wherein the memory accessing circuit includes a first address decoder circuit coupled to the memory address circuit, the first address decoder circuit generating first decoded signals in response to a first part of the memory address and including a third accessing circuit coupled to the dynamic memory and to the first address decoder circuit, the third accessing circuit accessing the plurality of data bits from the dynamic memory in response to the first decoded signals; and

wherein the dynamic memory system further comprises;

a second address decoder circuit coupled to the memory address circuit, the second address decoder circuit generating second decoded signals in response to a second part of the memory address;

a fourth accessing circuit coupled to the memory accessing circuit, to the second clock circuit, and to the second address decoder circuit, the fourth accessing circuit operating in response to the second clock signal and the second decoded signals to access one of the plurality of data bits accessed by the memory accessing circuit; and

an output circuit coupled to the second accessing circuit, the output circuit outputting the accessed one of the plurality of data bits.

43. A dynamic memory system as set forth in claim 41,

wherein the dynamic memory system further comprises:

a first clock circuit generating a first clock signal, wherein the memory address circuit is coupled to the first clock circuit and is adapted to generate the memory address in response to the first clock signal;

a second clock circuit generating a second clock signal;

a multiple data bit accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the multiple data bit accessing circuit operating in response to the second clock signal to access a plurality of the data bits accessed from the dynamic memory by the memory accessing circuit; and

an output shifting circuit coupled to the multiple data bit accessing circuit, the output shifting circuit outputting a sequence of the plurality of data bits accessed by the multiple data bit accessing circuit.

44. A dynamic memory system as set forth in claim 41, wherein the dynamic memory system further comprises:

a first clock circuit generating a first clock signal, wherein the memory address circuit is coupled to the first clock circuit and is adapted to generate the memory address in response to the first clock signal;

a second clock circuit generating a second clock signal;

a second accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the memory accessing circuit; and

wherein the memory refresh circuit includes a refresh address counter circuit generating a refresh address and an address refresh circuit coupled to the refresh address counter circuit, the address refresh circuit refreshing the data bits stored by the dynamic memory in response to the refresh address.

45. A dynamic memory system as set forth in claim 41,

wherein the dynamic memory system further comprises a first clock circuit generating a first clock signal and a second clock circuit generating a second clock signal;

wherein the memory address circuit is coupled to the first clock circuit and is adapted to generate the memory address in response to the first clock signal;

wherein the dynamic memory system further comprises a second accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the memory accessing circuit;

wherein the data bits include instruction data bits and operand data bits;

wherein the dynamic memory system further comprises a stored program computer coupled to the second accessing circuit, the stored program computer processing an operand data bit accessed by the second accessing circuit in response to an instruction data bit accessed by the second accessing circuit; and

wherein the memory refresh circuit includes a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory, the synchronized refresh circuit refreshing the data bits stored by the dynamic memory in synchronization with the processing of the data bit by the stored program computer.

46. A dynamic memory system as set forth in claim 41,

wherein the dynamic memory includes a plurality of pages of dynamic memory, each page having at least one of the plurality of dynamic integrated circuit memory chips;

wherein the dynamic memory system further comprises paging logic generating a page select signal to select one of the plurality of pages of dynamic memory; and

wherein the chip select circuit is further coupled to the paging logic and further operates in response to the page select signal to select the at least one but not all of the plurality of dynamic integrated circuit memory chips from the selected page of dynamic memory.

47. A dynamic memory as set forth in claim 41, wherein the plurality of dynamic integrated circuit memory chips are partitioned into a main memory having at least one of the dynamic integrated circuit memory chips, the main memory storing instruction data bits and operand data bits, and a scratch pad memory having at least one of the dynamic integrated circuit memory chips, the scratch pad memory storing operand data bits;

and

wherein the dynamic memory system further comprises a stored program computer coupled to the memory accessing circuit, the stored program computer processing an operand data bit output by the plurality of memory output circuits in response to an instruction data bit output by the plurality of memory output circuits.

48. A dynamic memory system comprising:

a dynamic memory storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit generating a memory address;

a first access circuit coupled to the dynamic memory, to the memory address circuit, and to the first clock circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address and in response to the first clock signal;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit;

a refresh address counter generating a refresh address; and

a memory refresh circuit coupled to the dynamic memory and to the refresh address counter and refreshing the digital data bits stored by the dynamic memory in response to the refresh address.

49. A dynamic memory system as set forth in claim 48, wherein the second access circuit is further coupled to the memory address circuit and further operates in response to the memory address to access one of the plurality of digital data bits accessed from the dynamic memory by the first access circuit.

50. A dynamic random access memory system comprising:

a dynamic memory for storing a plurality of digital data bits;

a first clock circuit generating a first clock signal;

a second clock circuit generating a second clock signal;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first access circuit coupled to the dynamic memory and to the memory address circuit and randomly accessing a plurality of digital data bits in the dynamic memory in response to the memory address;

a multiple digital data bit access circuit coupled to the first access circuit and to the second clock circuit and accessing a plurality of the digital data bits randomly accessed in the dynamic memory by the first access circuit in response to the second clock signal;

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory; and

an output circuit coupled to the second access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit.

51. A dynamic memory system as set forth in claim 50, wherein the multiple digital data bit access circuit is further coupled to the memory address circuit and further operates in response to the memory address to access one of the plurality of digital data bits accessed from the dynamic memory by the first access circuit.

52. A dynamic memory system comprising:

a dynamic memory storing data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory;

a first clock circuit generating a first clock signal;

a second clock circuit generating a second clock signal;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the first memory accessing circuit randomly accessing a plurality of data bits stored by the dynamic memory in response to the memory address;

a shift register circuit coupled to the first memory accessing circuit the shift register circuit outputting a one bit wide sequence of the plurality of data bits random accessed by the first memory accessing circuit; and

a second accessing circuit coupled to the first memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the first memory accessing circuit.

53. A dynamic memory system as set forth in claim 52, wherein the second access circuit is further coupled to the memory address circuit and further operates in response to the memory address to access one of the plurality of digital data bits accessed from the dynamic memory by the first access circuit.

54. A dynamic memory system comprising:

a dynamic memory storing data bits;

a first clock circuit generating a first clock signal;

a memory address circuit coupled to the first clock circuit, the memory address circuit generating a memory address in response to the first clock signal;

a second clock circuit generating a second clock signal;

a first memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the first memory address circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address;

a second accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the second accessing circuit operating in response to the second clock signal to access one of the plurality of data bits accessed by the memory accessing circuit;

a shift register circuit coupled to the memory accessing circuit, the shift register circuit outputting a sequence of the plurality of data bits accessed by the memory accessing circuit;

a refresh address counter circuit generating a refresh address; and

a memory refresh circuit coupled to the refresh address counter circuit and to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory in response to the refresh address.

55. A dynamic memory system as set forth in claim 54, wherein the second access circuit is further coupled to the memory address circuit and further operates in response to the memory address to access one of the plurality of digital data bits accessed from the dynamic memory by the first access circuit.

56. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips each dynamic integrated circuit memory chip storing a plurality of digital data bits;

a first clock circuit generating a first clock signal;

a second clock circuit generating a second clock signal;

a memory address circuit generating a memory address;

a first access circuit coupled to the dynamic memory, to the memory address circuit, and to the first clock circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address and in response to the first clock signal;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit;

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory;

a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit and selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; and

a plurality of memory output circuits coupled to the second access circuit and outputting the digital data bit accessed by the second access circuit from a selected one of the plurality of dynamic integrated circuit memory chips as a memory output signal on a conductor that is common to the plurality of dynamic integrated circuit memory chips.

57. A dynamic memory system as set forth in claim 56, wherein the second access circuit is further coupled to the memory address circuit and further operates in response to the memory address to access one of the plurality of digital data bits accessed from the dynamic memory by the first access circuit.

58. A dynamic memory system comprising:

a dynamic memory for storing a plurality of digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a second clock circuit generating a second clock signal having a second clock period;

a memory access circuit coupled to the dynamic memory and to the memory address circuit and accessing a plurality of digital data bits stored by the dynamic memory in response to the memory address; and

a selection circuit coupled to the memory access circuit and to the second clock circuit and operating in response to the second clock signal to select at least one but not all of the digital data bits accessed in the dynamic memory by the memory access circuit.

59. A dynamic memory system comprising:

a dynamic memory for storing digital data bits including instruction digital data bits and operand digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first access circuit coupled to the dynamic memory and to the memory address circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit;

a stored program computer coupled to the second access circuit and processing an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit; and

a memory refresh circuit coupled to the stored program computer and to the dynamic memory and refreshing digital data bits stored by the dynamic memory in response to the processing of the digital data bit by the stored program computer.

60. A dynamic memory system comprising:

a dynamic memory storing a plurality of digital data bits;

a first clock circuit generating a first clock signal;

a second clock circuit generating a second clock signal;

a memory address circuit generating a memory address;

a first access circuit coupled to the dynamic memory, to the memory address circuit, and to the first clock circuit, the first access circuit accessing a plurality of digital data bits in the dynamic memory in response to the memory address and in response to the first clock signal;

a multiple digital data bit access circuit coupled to the first access circuit and to the second clock circuit and accessing a plurality of the digital data bits accessed in the dynamic memory by the first access circuit in response to the second clock signal;

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory; and

an output circuit coupled to the second access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit.

61. A dynamic memory system comprising:

a dynamic memory storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first access circuit coupled to the dynamic memory and coupled to receive the memory address and accessing a plurality of digital data bits in the dynamic memory in response to the memory address;

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory;

a multiple digital data bit access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access a plurality of the digital data bits accessed in the dynamic memory by the first access circuit;

an output shifting circuit coupled to the multiple digital data bit access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit; and

a display monitor coupled to the output shifting circuit and displaying data in response to the plurality of digital data bits output by the output shifting circuit.

62. A dynamic random access memory system comprising:

a dynamic memory storing digital data bits including instruction digital data bits and operand digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first access circuit coupled to the dynamic memory and to the memory address circuit and randomly accessing a plurality of digital data bits in the dynamic memory in response to the memory address;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits randomly accessed in the dynamic memory by the first access circuit;

a stored program computer coupled to the second access circuit and processing an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit;

a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory and refreshing the digital data bits stored by the dynamic memory in synchronization with the processing of the operand digital data bit by the stored program computer.

63. A dynamic memory system comprising:

a dynamic memory storing digital data bits in a plurality of pages of dynamic memory;

a paging logic circuit coupled to the plurality of pages of dynamic memory to select one of the plurality of pages of dynamic memory;

a first clock circuit generating a first clock signal having a first a clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit generating a memory address;

a first access circuit coupled to the dynamic memory, to the memory address circuit, to the first clock circuit, and to the paging logic circuit, the first access circuit operating in response to the memory address and in response to the first clock signal to access a plurality of digital data bits from the page of dynamic memory selected by the paging logic circuit;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit; and

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.

64. A dynamic memory system comprising;

a dynamic main memory storing a plurality of digital data bits including instruction digital data bits and operand digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit generating a memory address;

a first access circuit coupled to the dynamic main memory, to the memory address circuit, and to the first clock circuit, the first access circuit accessing a plurality of digital data bits in the dynamic main memory in response to the memory address and in response to the first clock signal;

a second access circuit coupled to the first access circuit and to the second clock circuit, the second access circuit operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic main memory by the first access circuit;

a memory refresh circuit coupled to the dynamic main memory and refreshing the instruction digital data bits and the operand digital data bits stored by the dynamic main memory; and

a stored program computer coupled to the second access circuit and processing an operand digital data bit accessed by the second access circuit in response to an instruction digital data bit accessed by the second access circuit.

65. A dynamic memory system comprising:

a plurality of pages of dynamic memory storing digital data bits;

a paging logic circuit generating a page select signal to select one of the plurality of pages of dynamic memory;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit generating a memory address;

a first access circuit coupled to the dynamic memory, to the memory address circuit, to the first clock circuit, and to the paging logic circuit, the first access circuit operating in response to the memory address, in response to the first clock signal, and in response to the page select signal to access a plurality of digital data bits in the page of dynamic memory selected by the paging logic;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit; and

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.

66. A dynamic memory comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each said dynamic integrated circuit memory chip storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period that is shorter than the first clock period of the first clock signal;

a memory address circuit for generating a memory address;

a first access circuit coupled to the dynamic memory, to the memory address circuit, and to the first clock circuit and accessing a plurality of digital data bits in the dynamic memory in response to the memory address and in response to the first clock signal;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits accessed by the first access circuit;

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory;

a decoder circuit coupled to the memory address circuit and generating memory chip select signals in response to the memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit and selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; and

a plurality of memory output circuits coupled to the second access circuit and outputting the digital data bit accessed by the second access circuit in a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line common to the plurality of dynamic integrated circuit memory chips.

67. A dynamic random access memory system comprising:

a dynamic memory for storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first access circuit coupled to the dynamic memory and to the memory address circuit and randomly accessing a plurality of digital data bits from the dynamic memory in response to the memory address;

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory;

a multiple digital data bit access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access a plurality of the digital data bits randomly accessed in the dynamic memory by the first access circuit;

an output shifting circuit coupled to the multiple digital data bit access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit; and

a display monitor coupled to the output shifting circuit and displaying data in response to the plurality of digital data bits output by the output shifting circuit.

68. A dynamic random access memory system implemented on a single integrated circuit chip comprising:

a dynamic memory for storing digital data bits, wherein the dynamic memory is implemented on the single integrated circuit chip;

a first clock circuit generating a first clock signal having a first clock period, wherein the first clock circuit is implemented on the single integrated circuit chip;

a second clock circuit generating a second clock signal having a second clock period, wherein the second clock circuit is implemented on the single integrated circuit chip;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal, wherein the memory address circuit is implemented on the single integrated circuit chip;

a first access circuit coupled to the dynamic memory and to the memory address circuit and randomly accessing a plurality of digital data bits in the dynamic memory in response to the memory address, wherein the first access circuit is implemented on the single integrated circuit chip;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access one of the plurality of digital data bits that were randomly accessed in the dynamic memory by the first access circuit, wherein the second access circuit is implemented on the single integrated circuit chip;

a refresh address counter generating a refresh address, wherein the refresh address counter is implemented on the single integrated circuit chip; and

a memory refresh circuit coupled to the dynamic memory and to the refresh address counter and refreshing the digital data bits stored by the dynamic memory in response to the refresh address, wherein the memory refresh circuit is implemented on the single integrated circuit chip.

69. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period that is shorter than the first clock period of the first clock signal;

a memory address circuit generating a memory address;

a decoder circuit coupled to the memory address circuit and generating memory chip select signals in response to the memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit and selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals;

a first access circuit coupled to the dynamic memory and to the first clock circuit and accessing a plurality of digital data bits in the dynamic memory in response to the first clock signal;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access in sequence at least two of the plurality of digital data bits in sequence accessed by the first access circuit;

a plurality of memory output circuits coupled to the second access circuit and sequentially outputting the at least two of the plurality of digital data bits accessed by the second access circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line that is common to the plurality of dynamic integrated circuit memory chips; and

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.

70. A dynamic memory system comprising:

a dynamic memory storing digital data bits in a plurality of pages of dynamic memory;

a paging logic circuit generating a page select signal to select one of the plurality of pages of dynamic memory;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period that is shorter than the first clock period of the first clock signal;

a memory address circuit generating a memory address;

a first access circuit coupled to the dynamic memory to the memory address circuit, to the first clock circuit and to the paging logic and accessing a plurality of digital data bits in the page of dynamic memory that is selected by the paging logic in response to the memory address and in response to the first clock signal;

a second access circuit coupled to the first access circuit and to the second clock circuit and operating in response to the second clock signal to access in sequence at least two of the plurality of digital data bits accessed by the first access circuit; and

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.

71. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit that is coupled to the first clock circuit and generates a memory address in response to the first clock signal;

a first address decoder circuit coupled to the memory address circuit and generating first decoded signals in response to a first part of the memory address;

a first access circuit coupled to the dynamic memory and to the first address decoder circuit and randomly accessing a plurality of digital data bits in the dynamic memory in response to the first clock signal and the first decoded signals;

a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address;

a second access circuit coupled to the first access circuit, to the second clock circuit and to the second address decoder circuit and operating in response to the second clock signal and the second decoded signals to randomly access one of the plurality of digital data bits accessed in the dynamic memory by the first access circuit;

an output circuit coupled to the second access circuit and outputting the accessed one of the plurality of digital data bits;

a memory refresh circuit coupled to the dynamic memory and refreshing the digital bits stored by the dynamic memory;

a chip decoder circuit coupled to the memory address circuit and generating memory chip select signals in response to the memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the chip decoder circuit and selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; and

a plurality of memory output circuits coupled to the second access circuit and outputting the digital data bit accessed by the second access circuit in a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line that is common to the plurality of dynamic integrated circuit memory chips.

72. A dynamic memory system comprising:

a dynamic memory for storing digital data bits;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first address decoder circuit coupled to the memory address circuit and generating first decoded signals in response to a first part of the memory address;

a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address;

a first access circuit coupled to the dynamic memory and to the first address decoder circuit and randomly accessing a plurality of digital data bits from the dynamic memory in response to the first clock signal;

a multiple digital data bit access circuit coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit and accessing a plurality of the digital data bits accessed in the dynamic memory by the first access circuit in response to the second clock signal and the second decoded signals;

an output circuit coupled to the multiple digital data bit access circuit and outputting the plurality of digital data bits accessed by the multiple digital data bit access circuit;

a memory refresh circuit coupled to the dynamic memory and refreshing the digital bits stored by the dynamic memory; and

an output shifting circuit coupled to the multiple digital data bit access circuit and outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit.

73. A dynamic memory system comprising:

a dynamic memory storing digital data bits in a plurality of pages of dynamic memory;

a first clock circuit generating a first clock signal having a first clock period;

a second clock circuit generating a second clock signal having a second clock period;

a memory address circuit coupled to the first clock circuit and generating a memory address in response to the first clock signal;

a first address decoder circuit that is coupled to the memory address circuit and generates first decoded signals in response to a first part of the memory address;

a paging logic circuit generating a page select signal to select one of the plurality of pages of dynamic memory;

a first access circuit coupled to the dynamic memory, to the first address decoder circuit, and to the paging logic circuit and operating in response to the first decoded signals and in response to the page select signal to access a plurality of digital data bits in the page of dynamic memory that is selected by the paging logic;

a second address decoder circuit coupled to the memory address circuit and generating second decoded signals in response to a second part of the memory address;

a second access circuit coupled to the first access circuit, to the second clock circuit, and to the second address decoder circuit and operating in response to the second clock signal and the second decoded signals to access one of the plurality of digital data bits accessed by the first access circuit;

an output circuit coupled to the second access circuit and outputting the accessed one of the plurality of digital data bits; and

a memory refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.

74. A dynamic memory system comprising:

a dynamic memory including a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a first memory address circuit generating a first memory address;

a first address decoder circuit coupled to receive the first memory address from the first memory address circuit and generate first decoded signals in response to the first memory address;

a first access circuit coupled to receive the first decoded signals from the first address decoder circuit and coupled to the dynamic memory, the first access circuit random accessing a plurality of digital data bits stored by the dynamic memory in response to the first decoded signals;

a second memory address circuit generating a second memory address;

a second address decoder circuit coupled to receive the second memory address from the second memory address circuit and generate second decoded signals in response to the second memory address;

a second access circuit coupled to the first access circuit and coupled to receive the second decoded signals from the second address decoder circuit, the second access circuit operating in response to the second decoded signals to select one of the plurality of digital data bits accessed by the first access circuit;

third memory address circuit generating a third memory address;

a third address decoder circuit coupled to receive the third memory address from the third memory address circuit and generate memory chip select signals in response to the third memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive the memory chip select signals from the third address decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals;

a memory output signal conductor coupled to each of the dynamic integrated circuit memory chips;

a plurality of memory output circuits coupled to the second access circuit and outputting the digital data bit selected by the second access circuit from the selected at least one of the plurality of dynamic integrated circuit memory chips onto the memory output signal conductor; and

a refresh circuit coupled to the dynamic memory and refreshing the digital data bits stored by the dynamic memory.

75. A dynamic memory system comprising:

a dynamic memory adapted to store digital data bits;

a first memory address circuit generating a first memory address;

a first address decoder circuit coupled to the first memory address circuit, the first address decoder circuit generating first decoded signals in response to the first memory address;

a first access circuit coupled to the first address decoder circuit and to the dynamic memory, the first access circuit accessing a plurality of digital data bits stored by the dynamic memory in response to the first decoded signals;

a second memory address circuit generating a second memory address;

a second address decoder circuit coupled to the second memory address circuit, the second address decoder circuit generating second decoded signals in response to the second memory address;

a multiple digital data bit access circuit coupled to the first access circuit and to the second address decoder circuit, the multiple digital data bit access circuit operating in response to the second decoded signals to select a plurality of the digital data bits accessed by the first access circuit;

an output circuit coupled to the multiple digital data bit access circuit, the output circuit outputting a sequence of the plurality of digital data bits accessed by the multiple digital data bit access circuit; and

a refresh circuit coupled to the dynamic memory, the refresh circuit refreshing the digital data bits stored by the dynamic memory.

76. A dynamic memory system comprising:

a dynamic memory adapted to store digital data bits;

a first address circuit generating a first memory address;

a first address decoder circuit coupled to receive the first memory address from the first memory address circuit, the first address decoder circuit generating first decoded signals in response to the first memory address;

a first access circuit coupled to receive the first decoded signals from the first address decoder circuit and coupled to the dynamic memory, the first access circuit accessing a plurality of digital data bits stored by the dynamic memory in response to the first decoded signals;

a second memory address circuit generating a second memory address;

a second address decoder circuit coupled to receive the second memory address from the second memory address circuit, the second address decoder circuit generating second decoded signals in response to the second memory address generated by the second memory address circuit;

a second access circuit coupled to receive the plurality of digital data bits accessed by the first access circuit and coupled to receive the second decoded signals from the second address decoder circuit, the second access circuit operating in response to the second decoded signals to select one of the plurality of digital data bits accessed by the first access circuit;

an output circuit coupled to the second access circuit, the output circuit outputting the selected digital data bit;

a refresh address counter generating a refresh address; and

a memory refresh circuit coupled to receive a refresh address from the refresh address counter, the memory refresh circuit refreshing the digital data bits stored by the dynamic memory in response to the refresh address.

77. A dynamic memory system comprising:

a dynamic memory storing data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory;

a memory address circuit generating a memory address;

a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address; and

a shift register circuit coupled to the memory accessing circuit, the shift register circuit outputting a bit serial sequence of the plurality of data bits accessed by the memory accessing circuit.

78. A dynamic memory system comprising:

a dynamic memory storing data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory;

a memory address circuit generating a memory address;

a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address;

a shift register circuit coupled to the memory accessing circuit, the shift register circuit storing and outputting a sequence of the plurality of data bits accessed by the memory accessing circuit; and

a refreshable display coupled to the shift register circuit, the refreshable display generating a refreshed image in response to the sequence of data bits generated and outputted by the shifting circuit.

79. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory;

a memory address circuit generating a memory address;

a memory accessing circuit coupled to the dynamic memory and coupled to receive the memory address from the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address;

a shift register circuit coupled to the memory accessing circuit, the shift register circuit storing and outputting a sequence of the plurality of data bits accessed by the memory accessing circuit;

a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; and

a plurality of memory output circuits coupled to the memory accessing circuit, each memory output circuit outputting at least one of the data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips as a memory output signal on a conductor common to the plurality of dynamic integrated circuit memory chips.

80. A dynamic memory system comprising:

a dynamic memory storing a plurality of data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory;

a first clock circuit generating a first clock signal;

a second clock circuit generating a second clock signal;

a memory address circuit coupled to the first clock circuit, the memory address circuit generating a memory address in response to the first clock signal;

a first address decoder circuit coupled to the memory address circuit, the first address decoder circuit generating first decoded signals in response to a first part of the memory address;

a second accessing circuit coupled to the dynamic memory and to the first address decoder circuit, the second accessing circuit accessing the plurality of data bits from the dynamic memory in response to the first decoded signals;

a second address decoder circuit coupled to the memory address circuit, the second address decoder circuit generating second decoded signals in response to a second part of the memory address;

a third accessing circuit coupled to a memory accessing circuit, to the second clock circuit, and to the second address decoder circuit, the third accessing circuit operating in response to the second clock signal and the second decoded signals to access one of the plurality of data bits accessed by the memory accessing circuit;

an output circuit coupled to the second accessing circuit, the output circuit outputting the accessed one of the plurality of data bits;

the memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address; and

a shift register circuit coupled to the memory accessing circuit, the shift register circuit outputting a sequence of the plurality of data bits accessed by the memory accessing circuit.

81. A dynamic memory system comprising:

a dynamic memory storing data bits

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory;

a memory address circuit generating a memory address;

a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing from the dynamic memory a plurality of data bits stored by the dynamic memory in response to the memory address;

a shift register circuit coupled to the memory accessing circuit, the shift register circuit shifting out a sequence of the plurality of data bits accessed by the memory accessing circuit;

a first clock circuit generating a first clock signal, wherein the memory address circuit is coupled to the first clock circuit and is adapted to generate the memory address in response to the first clock signal;

a second clock circuit generating a second clock signal;

a multiple data bit accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the multiple data bit accessing circuit operating in response to the second clock signal to access a plurality of the data bits accessed from the dynamic memory by the memory accessing circuit; and

an output shifting circuit coupled to the second accessing circuit, the output shifting circuit outputting a sequence of the plurality of data bits accessed by the multiple data bit accessing circuit.

82. A dynamic memory system comprising:

a dynamic memory storing data bits including instruction data bits and operand data bits;

a memory address circuit generating a memory address;

a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address;

a shift register circuit coupled to the memory accessing circuit, the shift register circuit shifting out a sequence of the plurality of data bits accessed by the memory accessing circuit;

a first clock circuit generating a first clock signal;

a second clock circuit generating a second clock signal;

the memory address circuit being coupled to the first clock circuit, the memory address circuit generating the memory address in response to the first clock signal;

a second accessing circuit coupled to the memory accessing circuit and to the second clock signal, the second accessing circuit accessing one of the plurality of data bits accessed by the memory accessing circuit;

a stored program computer coupled to the second accessing circuit, the stored program computer processing an operand data bit accessed by the second accessing circuit in response to an instruction data bit accessed by the second accessing circuit; and

a synchronized refresh circuit coupled to the stored program computer and to the dynamic memory, the synchronized refresh circuit refreshing the data bits stored by the dynamic memory in synchronization with the processing of the data bit by the stored program computer.

83. A dynamic memory system comprising:

a dynamic memory including a plurality of pages of dynamic memory storing data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory;

a memory address circuit generating a memory address;

a paging logic circuit generating a page select signal that is coupled to each of the plurality of pages of dynamic memory and selects one of the plurality of pages of dynamic memory;

a memory accessing circuit coupled to the dynamic memory and to the paging logic circuit, the memory accessing circuit accessing a plurality of digital data bits from the page of dynamic memory that is selected by the paging logic in response to the memory address; and

a shift register circuit coupled to receive the plurality of data bits from the memory accessing circuit, the shift register circuit shifting out a sequence of the plurality of data bits accessed by the memory accessing circuit.

84. A dynamic memory system comprising:

a dynamic main memory storing instruction data bits and operand data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the dynamic memory;

a memory address circuit generating a memory address;

a memory accessing circuit coupled to the dynamic memory and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the dynamic memory in response to the memory address;

a shift register circuit coupled to the memory accessing circuit, the shift register circuit outputting a sequence of the plurality of data bits accessed by the memory accessing circuit; and

a stored program computer coupled to the memory accessing circuit, the stored program computer processing an operand data bit accessed by the memory accessing circuit in response to an instruction data bit accessed by the memory accessing circuit.

85. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips;

a memory address circuit generating a memory address;

a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals;

a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the selected at least one of the dynamic integrated circuit memory chips in response to the memory address;

a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal that is selectively coupled to each of the plurality of dynamic integrated circuit memory chips;

a shift register coupled to the memory accessing circuit, the shift register outputting a serial sequence of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips; and

a refreshable display coupled to the shift register, the refreshable display generating a refreshed image in response to the serial sequence of the plurality of data bits.

86. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips;

a first clock circuit generating a first clock signal;

a memory address circuit coupled to the first clock circuit, the memory address circuit generating a memory address in response to the first clock signal;

a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select, signals in response to the memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals;

a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and to the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by at least one of the dynamic integrated circuit memory chips in response to the memory address;

a second clock circuit generating a second clock signal;

a multiple data bit accessing circuit coupled to the memory accessing circuit and to the second clock circuit, the multiple data bit accessing circuit operating in response to the second clock signal to access a plurality of the data bits that were accessed from the dynamic memory by the memory accessing circuit;

a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line common to the plurality of dynamic integrated circuit memory chips; and

an output shifting circuit coupled to the multiple data bit accessing circuit, the output shifting circuit outputting a sequence of the plurality of data bits accessed by the multiple data bit accessing circuit.

87. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a memory refresh circuit coupled to the dynamic memory, the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips;

a memory address circuit generating a memory address;

a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory address;

a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and to the memory address circuit and accessing a plurality of data bits stored by at least one of the dynamic integrated circuit memory chips in response to the memory address;

a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal that is selectively coupled to each of the plurality of dynamic integrated circuit memory chips;

a shift register coupled to the memory accessing circuit, the shift register outputting a serial sequence of the plurality of data bits accessed by the memory accessing circuit from the selected one of the plurality of dynamic integrated circuit memory chips; and

a refreshable display coupled to the shift register, the refreshable display generating a refreshed image in response to the serial sequence of the plurality of data bits.

88. A dynamic memory system comprising:

a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits;

a memory refresh circuit coupled to the dynamic memory, and refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips;

a first clock circuit generating a first clock signal;

a memory address circuit coupled to receive the first clock signal from the first clock circuit and generating a memory address in response to the received first clock signal;

a second clock circuit generating a second clock signal;

a decoder circuit coupled to receive a memory address from the memory address circuit, the decoder circuit generating memory chip select signals in response to the received memory address;

a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive memory chip select signals from the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the received memory chip select signals;

a first memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive a memory address from the memory address circuit, the first memory accessing circuit accessing a plurality of data bits stored by at least one of the dynamic integrated circuit memory chips in response to the received memory address;

a second memory accessing circuit coupled to the first memory accessing circuit and coupled to receive the second clock signal from the second clock circuit, the second memory accessing circuit operating in response to the received second clock signal to access one of the plurality of data bits accessed by the first memory accessing circuit; and

a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal line common to the plurality of dynamic integrated circuit memory chips.