Method and apparatus for mapping memory as to operable and faulty locations

• US 5,541,938 A
• Filed: 03/11/1994
• Issued: 07/30/1996
• Est. Priority Date: 03/12/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Di Zenzo, Maurizio, Salsano, Adelio, Pistilli, Pasquale
• Primary Examiner(s): Gordon, Paul P.
• Assistant Examiner(s): Garland, Steven R.
• Application Number:
  US08/209,580
• Time in Patent Office: 872 Days
• Field of Search: 371/10.1-10.3, 371/11.1, 371/21.6, 371/40.1, 365/200, 365/201, 365/230.3, 365/230.6, 364/DIG. 1, 395/182.03-182.06, 395/412
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

System for enabling the use of semiconductor dynamic memories having faulty locations therein where the memory is organized in banks for forming an elementary information word. The system identifies all homologous address locations which are not faulty, and the non-faulty locations are then stored as a map in a non-volatile read-only-memory related to the memory bank so as to form a transcoding table. Access to the memory blocks involves the use of a central processing unit requesting access to a block identified by a sequential address. The system then provides for associating the material address of a block of the memory array to the logical address, this association or transcoding operation being carried out by the non-volatile read-only-memory.

Claims

1. A method for mapping operable homologous address locations in a semiconductor memory device having faulty locations so as to enable such semiconductor memory devices to be used, said method comprising:

organizing the semiconductor memory device as at least one memory block having a plurality of memory banks to form an elementary information word;

identifying all operable homologous address locations of the memory banks of the semiconductor memory device;

utilizing areas of the memory block having a limited number of faulty locations by applying an error correction procedure implementing a modified Reed-Solomon algorithm having a generator polynomial

space="preserve" listing-type="equation">g(x)=x.sup.4 +a.sup.201.x.sup.3 +a.sup.246.x.sup.2 +a.sup.201.x+1

by translating a data string in such a manner as to move an error always to the first location of the data string;

detecting and correcting errors by logic test circuits;

establishing a map of the operable homologous address locations of the memory banks;

storing the map of operable homologous address locations of the memory banks in a non-volatile memory as data content respectively associated with the memory bank, thereby forming a transcoding table of material addresses in the non-volatile memory;

requesting access to a memory block identified by a sequential logical address;

associating the sequential logical address of the memory block to a material address of the non-volatile memory;

retrieving the data content of a selected material address from the non-volatile memory; and

directly accessing the corresponding memory block enabled by the data content retrieved from the non-volatile memory at the selected material address.

2. A method as set forth in claim 1, wherein the data string includes data coefficients and control byte coefficients;

said method further including coding the data string to maintain the data coefficients separate from the control byte coefficients.

3. A method as set forth in claim 2, wherein coding of the data string is accomplished in accordance with the relationship

4. A method as set forth in claim 3, further including decoding the data string of a plurality of bytes to compute a syndrome S(x) in accordance with the following relationships

5. A method as set forth in claim 1, wherein a supply voltage is provided for the memory banks of the semiconductor memory device;

further including controlling voltage conditions relating to the supply voltage for the memory banks and the voltage levels for input signals to the semiconductor memory device during the mapping of the operable homologous address locations of the memory banks.

6. A method as set forth in claim 1, wherein mapping of the operable homologous address locations in the memory banks is carried out under ambient room temperature conditions of the order of 25°

C. and further under high temperature conditions of the order of 70°

C.

7. A semiconductor memory mapping system for use with a semiconductor memory device having operable and faulty locations therein, wherein the semiconductor memory device is organized as a plurality of memory blocks, each memory block having a plurality of memory banks in order to form an elementary information word, said memory mapping system comprising

means for organizing the operable and faulty locations in a memory block into a plurality of byte sub-strings from an individual byte string of the memory block, wherein each byte sub-string including a plurality of bytes is accompanied by a plurality of control bytes, there being a total of 36 characters in a composite unit character string including 32 characters of regular information and 4 characters for error control;

translation means operable upon a byte sub-string of regular characters and error control characters for transposing a detected error in the character string to the first location of the character string;

test control logic circuits for detecting an error located in the first location of the translated 36 character string and for correcting the error existing in the first location; and

said test control logic circuits being responsive to the identification of a polynomial expression indicative of the presence of an error in a byte string, the polynomial structure being in the form of a modified Reed-Solomon algorithm with a generator polynomial in the form

space="preserve" listing-type="equation">g(x)=x.sup.4 +a.sup.201.x.sup.3 +a.sup.246.x.sup.2 +a.sup.201.x+1.

8.

8. A memory mapping system as set forth in claim 7, further including a coder circuit for operating upon a respective 36-character string having data coefficient locations and control byte coefficients to maintain the data coefficient locations separate from the control byte coefficients in the 36-character string in accordance with the following mathematical relationships

9. A memory mapping system as set forth in claim 8, wherein said coder circuit comprises a ladder network having four transversal arms and two longitudinal legs forming opposite sides of the ladder network between which the four transversal arms extend, said coder circuit including

a first 8-bit exclusive-OR logic circuit in one transversal arm of the ladder network for receiving an input signal;

an output multiplexer circuit having first and second inputs, the first input of said output multiplexer circuit receiving the input signal;

an AND logic gate circuit included in a first longitudinal leg forming one side of the ladder network and having first and second inputs for respectively receiving a first selection signal and the output of said first exclusive-OR logic circuit;

respective 8-bit multiplier circuits provided in each of the remaining three transversal arms of said ladder network;

a second longitudinal leg forming the other side of the ladder network including four master-slave flip-flop circuits;

respective exclusive-OR logic circuits being disposed at nodes formed by the remaining three transversal arms and the second longitudinal leg forming the other side of said ladder network and alternating with said master-slave flip-flop circuits in the second longitudinal leg of said ladder network; and

the fourth flip-flop circuit disposed in the second longitudinal leg of said ladder network being connected to the second input of said output multiplexer circuit.

10. A memory mapping system as set forth in claim 7, further including a decoder circuit for correcting errors within a syndrome of four bytes, said decoder circuit including a first decoder block, a second decoder block and a third decoder block connected in cascade;

a first memory block of a first in-first out data memory connected in parallel with respect to said first decoder block;

a first exclusive-OR logic circuit connected to the output of said first memory block and the output of said second decoder block;

a first correction block interposed in the connection between the output of said second decoder block and said first exclusive-OR logic circuit;

a second memory block of a first in-first out memory;

the output of said first exclusive-OR logic circuit being connected to an input of said third decoder block and to said second memory block;

a second exclusive-OR logic circuit having an input connected to the output of said third decoder block and an input connected to the output of said second memory block; and

a second correction block interposed in the connection between the output of said third decoder block and an input of said second exclusive-OR logic circuit.

11. A memory mapping system as set forth in claim 10, wherein said first decoder block comprises:

a first set of four 8-bit multiplier circuits connected in parallel with respect to each other for receiving an input signal;

four exclusive-OR logic circuits having inputs for respectively receiving the output of a corresponding one of said four 8-bit multiplier circuits;

four master-slave flip-flop circuits respectively connected to the outputs of a corresponding one of said four exclusive-OR logic circuits;

a second set of three 8-bit multiplier circuits connected in parallel with respect to each other;

the output of the last one of said master-slave flip-flop circuits being connected directly to the first one of said four exclusive-OR logic circuits and to the remaining three exclusive-OR logic circuits via corresponding ones of said second set of three 8-bit multipliers; and

a multiplexer circuit having respective inputs for receiving the outputs of all of said master-slave flip-flop circuits.

12. A memory mapping system as set forth in claim 10, wherein said second decoder block comprises:

a first decoder block;

a set of identical decoder blocks and a further decoder block connected in parallel with respect to each other and to the output of said second decoder block;

a selection and correction block for receiving the outputs from said set of identical decoder blocks and said further decoder block; and

an exclusive-OR logic circuit having inputs for respectively receiving the output of said selection and correction block and a signal V(x) and providing an output signal V'"'"'(x).

13. A memory mapping system as set forth in claim 12, wherein said first decoder block of said second decoder block comprises:

a set of four double-state master-slave flip-flop circuits;

three exclusive-OR logic circuits, a corresponding one of said three exclusive-OR logic circuits being interconnected between successive double-state master-slave flip-flop circuits so as to provide alternating double-state master-slave flip-flop circuits and an exclusive-OR logic circuit;

the output of the last flip-flop circuit being connected directly to the first flip-flop circuit;

three 8-bit multiplier circuits connected in parallel with respect to each other and respectively connected to an input of a corresponding one of said three exclusive-OR logic circuits;

the output of the last flip-flop circuit being respectively connected to each of said three exclusive-OR logic circuits through the respective 8-bit multiplier circuit; and

each of said four flip-flop circuits being connected in parallel to receive the input signal.

14. A memory mapping system as set forth in claim 12, wherein said set of identical decoder blocks comprises

first and second sets of four input connections;

four exclusive-OR logic circuits coupled to said first set of four input connections;

four 8-bit multiplier circuits connected to said second set of four input connections and having respective outputs connected to a corresponding one of said four exclusive-OR logic circuits;

four NOR gate circuits respectively connected to the outputs of said four exclusive-OR logic circuits;

four AND logic gate circuits, a respective one of said four AND logic gate circuits having an input connected to the output of a corresponding one of said four NOR logic gate circuits; and

an OR logic gate circuit having inputs connected to the outputs of said four AND logic gate circuits.

15. A memory mapping system as set forth in claim 12, wherein said further decoder block comprises:

first, second, and third NOR logic gate circuits;

first, second, and third NAND logic gate circuits;

said first NOR logic gate circuit having an output connected to said first and third NAND logic gate circuits;

said second NOR logic gate circuit having an output connected to said first and second NAND logic gate circuits;

said third NOR logic gate circuit having an output connected to said second and third NAND logic gate circuits;

a fourth NAND logic gate circuit having three inputs respectively connected to the outputs of said first, second and third NAND logic gate circuits and providing a signal TANA as an output; and

an AND logic gate output circuit having first and second inputs respectively receiving the output signal TANA from said fourth NAND logic gate circuit and a signal S₄.sup.(r).

16. A memory mapping system as set forth in claim 10, wherein said third decoder block comprises:

four exclusive-OR logic gate circuits;

four master-slave flip-flop circuits interconnected with said four exclusive-OR logic circuits in an alternating sequence such that each of said four exclusive-OR logic circuits is followed by a master-slave flip-flop circuit;

four 8-bit multiplier circuits connected in parallel for receiving an input signal V'"'"'(x) and having outputs connected to an input of a corresponding one of said four exclusive-OR logic circuits;

a signal block for providing an output signal VERR having respective inputs for receiving the outputs of said four master-slave flip-flop circuits;

a further exclusive-OR logic circuit having an output connected to the first exclusive-OR logic circuit included in said four exclusive-OR logic circuits and to inputs of the remaining three exclusive-OR logic circuits;

three 8-bit multiplier circuits interposed in the connection between the output of said further exclusive-OR logic circuit and the inputs of said remaining three exclusive-OR logic circuits; and

a final exclusive-OR logic circuit having an input connected to said signal block for receiving the output signal VERR and a second input for receiving a signal S'"'"'(x) and providing as an output a signal c(x)=d(x)+t(x), wherein

S'"'"'(x) is a syndrome signal,

c(x) is the coded data,

d(x) is the data included in the data string, and

t(x) is an error control.