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Data processing system with duplex common memory having physical and logical path disconnection upon failure

  • US 5,548,743 A
  • Filed: 05/24/1994
  • Issued: 08/20/1996
  • Est. Priority Date: 05/18/1990
  • Status: Expired due to Term
First Claim
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1. A data processing system, comprising:

  • two common memories comprising a duplex memory;

    processors each accessing said common memories and detecting whether said common memories are valid or invalid with invalid indicating the common memories have a failure;

    input/output paths separately connecting said common memories and said processors; and

    input/output path disconnecting means for physically disconnecting said input/output paths from said invalid common memories to all said processors upon indication of invalidity,each of said processors comprising;

    control information storing means for storing control information showing whether each of said common memories is valid or invalid;

    input/output path disconnection processing means for writing control information, showing that a corresponding one of the common memories is invalid, into said control information storing means when said input/output path disconnection processing means is informed of an occurrence of the failure in one of said common memories by said processor and said control information for indicating to said input/output path disconnecting means to disconnect the input/output paths connected to said corresponding one of said common memories which is invalid; and

    access inhibit processing means for writing control information upon indication of physical disconnection determined via an access attempt, showing that said corresponding one of said common memories is disconnected, into corresponding control information storing means and when each of said processors, other than a one of said processors informed of the occurrence of the failure, has attempted access to said one of the common memories via said input/output paths which have been disconnected from said common memories by said input/output disconnecting means, said control information inhibiting further access attempts by said processors.

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