Data processing system with duplex common memory having physical and logical path disconnection upon failure
First Claim
1. A data processing system, comprising:
- two common memories comprising a duplex memory;
processors each accessing said common memories and detecting whether said common memories are valid or invalid with invalid indicating the common memories have a failure;
input/output paths separately connecting said common memories and said processors; and
input/output path disconnecting means for physically disconnecting said input/output paths from said invalid common memories to all said processors upon indication of invalidity,each of said processors comprising;
control information storing means for storing control information showing whether each of said common memories is valid or invalid;
input/output path disconnection processing means for writing control information, showing that a corresponding one of the common memories is invalid, into said control information storing means when said input/output path disconnection processing means is informed of an occurrence of the failure in one of said common memories by said processor and said control information for indicating to said input/output path disconnecting means to disconnect the input/output paths connected to said corresponding one of said common memories which is invalid; and
access inhibit processing means for writing control information upon indication of physical disconnection determined via an access attempt, showing that said corresponding one of said common memories is disconnected, into corresponding control information storing means and when each of said processors, other than a one of said processors informed of the occurrence of the failure, has attempted access to said one of the common memories via said input/output paths which have been disconnected from said common memories by said input/output disconnecting means, said control information inhibiting further access attempts by said processors.
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Abstract
A method is provided which controls a data processing system having two common memories forming a duplex memory, a plurality of clusters provided in common for the common memories, and input/output paths connecting the clusters to the common memories. The method includes the steps of detecting a failure which has occurred in one of the common memories by each of the clusters, physically disconnecting input/output paths connected to the above-mentioned one of the common memories therefrom when the failure is detected by one of the clusters, and inhibiting the clusters from accessing the above-mentioned one of the common memories in which the failure has occurred. There is also provided a data processing system that uses such a method.
40 Citations
10 Claims
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1. A data processing system, comprising:
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two common memories comprising a duplex memory; processors each accessing said common memories and detecting whether said common memories are valid or invalid with invalid indicating the common memories have a failure; input/output paths separately connecting said common memories and said processors; and input/output path disconnecting means for physically disconnecting said input/output paths from said invalid common memories to all said processors upon indication of invalidity, each of said processors comprising; control information storing means for storing control information showing whether each of said common memories is valid or invalid; input/output path disconnection processing means for writing control information, showing that a corresponding one of the common memories is invalid, into said control information storing means when said input/output path disconnection processing means is informed of an occurrence of the failure in one of said common memories by said processor and said control information for indicating to said input/output path disconnecting means to disconnect the input/output paths connected to said corresponding one of said common memories which is invalid; and access inhibit processing means for writing control information upon indication of physical disconnection determined via an access attempt, showing that said corresponding one of said common memories is disconnected, into corresponding control information storing means and when each of said processors, other than a one of said processors informed of the occurrence of the failure, has attempted access to said one of the common memories via said input/output paths which have been disconnected from said common memories by said input/output disconnecting means, said control information inhibiting further access attempts by said processors. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for controlling a data processing system which has two common memories comprising a duplex memory, processors provided in common for said common memories, and input/output paths separately connecting said processors to said common memories, said method comprising the steps of:
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storing data in the duplex memory; detecting, by one of said processors using the common memories, a defective memory failure which has occurred in one of said common memories; storing control information indicating the defective memory failure; physically disconnecting, via an access control device, all the input/output paths connected to said one of the common memories that has failed responsive to the control information; detecting a physical disconnection via an access attempt; and inhibiting access further attempts by said processors to said one of the common memories in which said failure has occurred responsive to the detecting of the physical disconnection. - View Dependent Claims (9)
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10. A data processing system, comprising:
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a common data device comprising a duplex memory; processors each accessing said common data device and each capable of detecting a fault in memories of said common data device and storing control information indicating the fault in control information storage means and including processing means for detecting the fault and writing the control information into said control information storage means; input/output paths separately connecting said common data device and said processors; input/output path disconnecting means for physically disconnecting said input/output paths from said memories with the fault memories to all said processors upon detecting of the fault; and an access control device connected to said common data device, said processors and said input/output path disconnecting means and controlling the data between said common data device and said processors, with said access control device physically disconnecting all the paths to said common data device when one of said processors detects a fault in said common data device responsive to said control information or upon command by one of said processors and detecting the physical disconnection via an access attempt and inhibiting further access attempts by said processors responsive to the detection of the physical disconnect, with all of said processors being disconnected from and inhibited from accessing said common data device by one of said processors.
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Specification