Signal processing circuit for switch capable of reducing insertion loss

• US 5,554,892 A
• Filed: 04/28/1994
• Issued: 09/10/1996
• Est. Priority Date: 04/28/1993
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Norimatsu, Hidehiko
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): PALADINI, ALBERT WILLIAM
• Application Number:
  US08/233,942
• Time in Patent Office: 866 Days
• Field of Search: 307/115, 327/431, 327/408, 327/355, 327/356, 455/135, 455/139, 455/143, 455/150.1
• US Class Current: 307/115
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

A high frequency power amplifier is implemented by a GaAs FET and is supplied with a positive and a negative power supply. The amplifier amplifies the power of an input signal and delivers the amplified signal to a high frequency switch. The high frequency switch is supplied switch control voltages in the form of the positive and negative voltages. Since the switch control voltages are implemented as the positive and negative voltages, a great difference in level between the switch control voltages is achievable which improves insertion loss. While the high frequency switch may also be implemented by GaAs FETs, the insertion loss will be further reduced if the negative voltage is applied to the high frequency switch only during transmission. In this case, current consumption will also be reduced if the generation of the negative voltage is controlled at the negative voltage source side.

Claims

1. A signal processing circuit for a switch comprising:

a switch having a plurality of routes to pass a signal; and

a first controller, to select one of the routes, for supplying a positive voltage and a negative voltage as switch control signals to said switch in response to a control signal.

2. The circuit as claimed in claim 1, said circuit further comprising:

at least one amplifier, supplied with the negative voltage and the positive voltage, for supplying an amplified signal to said switch;

at least one negative voltage generator for generating the negative voltage;

at least one positive voltage generator for generating the positive voltage; and

a second controller for supplying the control signal to said first controller.

3. The circuit as claimed in claim 1, wherein said first controller supplies either the negative voltage or a zero voltage selectively to said switch in response to the control signal applied by said second controller.

4. The circuit as claimed in claim 3, wherein said first controller is capable of supplying the negative voltage during a communication state or the zero voltage during a state other than the communication state.

5. The circuit as claimed in claim 3, wherein said first controller is capable of supplying the negative voltage during either a conversation state or a waiting for transmission state, while said first controller is capable of supplying the zero voltage during a state other than the conversation state and the waiting for transmission state.

6. The circuit as claimed in claim 2, said negative voltage generator further comprising:

a zero voltage generator for generating a zero voltage in response to the control signal from said second controller.

7. The circuit as claimed in claim 6, wherein said negative voltage generator supplies the negative voltage during a communication state or the zero voltage during a state other than the communication state.

8. The circuit as claimed in claim 6, wherein said negative voltage generator is capable of supplying the negative voltage during a conversation state and a waiting for transmission state, or the zero voltage during a state other than the conversation state and waiting for transmission state.

9. The circuit as claimed in claim 1, wherein said switch comprises GaAs FETs.

10. The circuit as claimed in claim 2, wherein said amplifier comprises a GaAs FET.

11. The circuit as claimed in claim 9, wherein said switch comprises:

a plurality of switching transistors, responsive to the switch control signals to gates thereof, for selectively passing the signal;

a plurality of terminating transistors connected between said plurality of switching transistors and a ground, and responsive to switch control signals to gates thereof and the positive voltage to the sources thereof; and

a plurality of capacitors connected between said source of said terminating transistors and the ground.

12. A signal processing circuit for a switch of a communication apparatus comprising:

amplifying means for supplying amplified signals;

switch having a plurality of routes to pass said amplified signals;

positive voltage generating means for generating a positive voltage and supplying said positive voltage to said amplifying means and said switch;

second voltage generating means for generating either a negative voltage or a zero voltage and supplying said voltage to said amplifying means and said switch;

first control means, to select one of said routes of said switch, for selectively supplying said positive voltage and said negative voltage as switch control signals to said switch in response to a first control signal; and

second control means for supplying said first control signal to said first control means.

13. The circuit as claimed in claim 12, wherein said positive voltage generating means supplies the positive voltage to said amplifying means and said switch selectively in response to said first control means.

14. A method for controlling a signal processing circuit for a switch, the method comprising the steps of:

(a) switching between a plurality of routes to pass a signal therethrough; and

(b) selecting one of said routes by supplying a first normally positive voltage and a second voltage to said switch as switch control signals in response to a control signal.

15. The method for controlling said circuit as claimed in claim 14, the method further comprising the steps of:

(c) selectively supplying between a negative voltage and a zero voltage as said second voltage.

16. A method for controlling a signal processing circuit in a communication apparatus, the method comprising:

(a) amplifying one or more input signals to generate one or more amplified input signals;

(b) switching between a plurality of routes for passage of said amplified input signals;

(c) selecting between said routes according to a switch control signal applied thereto, wherein a positive voltage is supplied to one or more of said routes while a second voltage is applied to the other of said routes.

17. The method for controlling said circuit as claimed in claim 16, wherein said switch control signal selectively supplies either a zero voltage or a negative voltage to said second voltage.