Programmable interconnect structures and programmable integrated circuits

• US 5,557,136 A
• Filed: 06/01/1992
• Issued: 09/17/1996
• Est. Priority Date: 04/26/1991
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Wong, Richard J., Gordon, Kathryn E.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/892,466
• Time in Patent Office: 1,569 Days
• Field of Search: 257/530, 257/50, 437/922
• US Class Current: 257/530
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Claims

1. A field programmable gate array comprising:

a first metal conductor;

an insulating layer overlaying the first metal conductor, the insulating layer having an opening formed therein;

a plug in the opening, the plug comprising tungsten, the plug contacting the first conductor, a top surface of the insulating layer having a portion adjacent the plug, the portion being substantially coplanar with a top surface of the plug;

amorphous silicon having a substantially planar bottom surface which overlays and contacts the plug and also overlays and contacts the adjacent portion of the insulating layer; and

a second metal conductor overlaying and contacting the amorphous silicon.