ESD protection improvement

  • US 5,559,352 A
  • Filed: 12/12/1994
  • Issued: 09/24/1996
  • Est. Priority Date: 10/22/1993
  • Status: Expired due to Term
First Claim
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1. An ESD protection device with reduced junction breakdown voltage, connected to an integrated circuit which includes FET devices, comprising:

  • a silicon substrate having a first conductivity type;

    field oxide regions in and on said silicon substrate for isolation of said ESD protection device;

    a gate with adjacent spacers for said ESD protection device, between said field oxide regions;

    source/drain regions for said ESD protection device between said gate and said field oxide regions, with each source/drain region comprising;

    a first lightly implanted region having a second conductivity type opposite to said first conductivity type, under one of said spacers;

    a heavier implanted region of the same conductivity type as said first lightly implanted region, located between said first lightly implanted region and one of said field oxide regions;

    a second lightly implanted region of same conductivity type as said silicon substrate, centered under said heavier implanted region.

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