Flash memory having select transistors

  • US 5,559,735 A
  • Filed: 03/28/1995
  • Issued: 09/24/1996
  • Est. Priority Date: 03/28/1995
  • Status: Expired due to Term
First Claim
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1. A flash type memory cell comprising:

  • a first transistor having a floating gate and a control gate stacked on a semiconductor substrate;

    a second transistor having gates stacked on one another with a drain diffusion layer of said first transistor as a source diffusion layer of said second transistor, said gates being made of the same materials as those of the floating gate and the control gate; and

    a memory cell each provided as a single unit, being composed of said first transistor and said second transistor;

    said second transistor being electrically connected to one another at a location different from that of said single-unit memory cell and activated as select gates;

    wherein the density of impurities of said drain diffusion layer of said second transistor, said impurities being provided in the neighborhood of the gate thereof, is lower than that of impurities of the drain diffusion layer of said first transistor, said impurities being provided in the neighborhood of the gate thereof.

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