Flash memory having select transistors

• US 5,559,735 A
• Filed: 03/28/1995
• Issued: 09/24/1996
• Est. Priority Date: 03/28/1995
• Status: Expired due to Term

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Ono, Takashi, Ikegami, Masami
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/412,276
• Time in Patent Office: 546 Days
• Field of Search: 365/185, 365/900, 365/218, 365/185.17, 365/185.33, 257/314, 257/315
• US Class Current: 365/185.3
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A plurality of stack type transistors each formed by successively stacking a tunnel oxide, a floating gate, an ONO stacked insulating film and a control gate on one another are provided on a silicon semiconductor substrate. A select transistor is provided adjacent to each of the stack type transistors. A flash memory cell is made up of two transistors: the stack type transistor and the select transistor. Owing to the present construction, a flash memory cell can be achieved which is operable at a low voltage, excellent in rewrite endurance, rewritable on a one-pulse basis and free from verification and overerasing cares. Accordingly, a high-reliable flash memory can be realized.

Claims

1. A flash type memory cell comprising:

a first transistor having a floating gate and a control gate stacked on a semiconductor substrate;

a second transistor having gates stacked on one another with a drain diffusion layer of said first transistor as a source diffusion layer of said second transistor, said gates being made of the same materials as those of the floating gate and the control gate; and

a memory cell each provided as a single unit, being composed of said first transistor and said second transistor;

said second transistor being electrically connected to one another at a location different from that of said single-unit memory cell and activated as select gates;

wherein the density of impurities of said drain diffusion layer of said second transistor, said impurities being provided in the neighborhood of the gate thereof, is lower than that of impurities of the drain diffusion layer of said first transistor, said impurities being provided in the neighborhood of the gate thereof.

2. A memory array comprising:

a plurality of flash type memory cells each of which comprises;

a first transistor having a floating gate and a control gate stacked on a semiconductor substrate;

a second transistor having gates stacked on one another with a drain diffusion layer of said first transistor as a source diffusion layer of said second transistor, said gates being made of the same materials as those of the floating gate and the control gate; and

a memory cell each provided as a single unit, being composed of said first transistor and said second transistor;

said second transistor being electrically connected to one another at a location different from that of said single-unit memory cell and activated as select gates;

a common source diffusion layer;

a plurality of control lines;

a plurality of select word lines; and

a plurality of bit lines;

said common source diffusion layer, said control lines, said select word lines and said bit lines being respectively formed by connecting source diffusion layers of said first transistors to one another in a first direction, connecting control gates of said first transistors to one another in the first direction, connecting gates of said second transistors to one another in the first direction and connecting metal interconnects coupled to the drain diffusion layers of said second transistors to one another in a second direction perpendicular to the first direction when a plurality of said memory cells are disposed; and

data erasing being performed by applying a positive voltage to the control line and storing electrons in the floating gate using an FN tunneling current supplied from a channel of said first transistor, data writing being performed by applying a negative voltage to the control line, applying a positive voltage to the select word line and applying a positive voltage to the bit line to thereby draw the electrons from the floating gate to the drain diffusion layer of said first transistor using the FN tunneling current, and data write prohibition being performed by setting the potential on the bit line to near a ground potential.

3. The memory array as claimed in claim 2, wherein the data erasing and writing are carried out on a one-operation basis without verifying a threshold value of each memory cell.