Dynamic random access memory with a simple test arrangement

  • US 5,559,739 A
  • Filed: 09/28/1995
  • Issued: 09/24/1996
  • Est. Priority Date: 09/28/1995
  • Status: Expired due to Fees
First Claim
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1. A Dynamic Random Access Memory (DRAM) including an array of memory cells arranged in rows and columns, a word line in each said row responsive to a row address, a pair of complementary bit lines in each said column, said DRAM further comprising:

  • a sense amp in each said column connected between a sense enable and said pair of complementary bit lines;

    a bit line pre-charge connected to each pair of complementary bit lines, said bit line pre-charge being connected between said complementary bit line pair and a reference voltage; and

    ,test control means for selectively holding said sense amp disabled and said bit line pairs in a pre-charge state responsive to a test control signal.

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