Memories with burst mode access

• US 5,559,990 A
• Filed: 10/24/1994
• Issued: 09/24/1996
• Est. Priority Date: 02/14/1992
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cheng, Pearl P., Briner, Michael S., Yu, James C.
• Primary Examiner(s): RUDOLPH, REBECCA
• Application Number:
  US08/328,337
• Time in Patent Office: 701 Days
• Field of Search: 395/425, 395/500, 395/484, 395/405, 395/421.07, 395/401, 395/481, 365/230, 365/230.04, 365/230.08, 365/238.5
• US Class Current: 711/157
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

To provide a boundaryless burst mode access, a memory array is divided into two or more subarrays. Each subarray has its own row and column decoders. The columns of each subarray are divided into groups. A sense amplifier circuit is provided for each group of columns. The column decoder of each subarray selects simultaneously one column from each group so that the memory locations in one row in the selected columns have consecutive addresses. The memory locations in the selected row and columns are read by the sense amplifier circuits. While the contents of the sense amplifier circuits of one subarray are transferred one by one to the memory output, consecutive memory locations of another subarray are read to the sense amplifier circuits. In some embodiments, to save power, sense amplifier circuits are disabled when their outputs are not transferred to the memory output.

Claims

1. A memory comprising:

a plurality of rows of memory locations;

a plurality of first registers, each first register for receiving a row address;

a plurality of row decoders, each row decoder for activating a portion of a row identified by signals from one of said first registers;

one or more sense amplifiers for amplifying contents of said memory locations in the row portions; and

an output for providing output signals from said sense amplifiers,

wherein at least two locations L1 and L2 in different rows having different row addresses in said memory can be read out to said output in burst mode such that the memory receives an address of one of said locations and provides in response contents of a plurality of memory locations, including the locations L1 and L2, in the sequence of consecutive addresses, so that while one of said row decoders is activating a row portion comprising said location L1 and contents of said location L1 are being transferred from one or more of said sense amplifiers to said output, another one of said row decoders is activating a row portion comprising said location L2 and contents of said location L2 are being transferred from said location L2 to one or more of said sense amplifiers.

2. The memory of claim 1, said memory having a random mode in which the memory receives an address and provides in response the contents of a unique memory location,

wherein, both in burst mode and in random mode, while the contents of said location L1 are being transferred from one or more of said sense amplifiers to said output, the contents of said location L2 are being transferred from said location L2 to one or more of said sense amplifiers.

3. The memory of claim 1 wherein when the locations L1 and L2 are read out in burst mode and when the contents of said location L1 are being transferred from one or more of said sense amplifiers to said output and the contents of said location L2 are being transferred from said location L2 to one or more of said sense amplifiers, the sense amplifiers from which the contents of said location L1 are being transferred are enabled and the sense amplifiers to which the contents of said location L2 are being transferred are disabled, but these latter sense amplifiers become enabled subsequently for amplifying the contents of said location L2.

4. The memory of claim 1 wherein:

said memory comprises k pluralities S-1, . . . , S-k of locations wherein k is a number of said pluralities and is greater than or equal to two;

for each plurality S-i, said sense amplifiers can receive simultaneously the contents of number m of locations from said plurality S-i, wherein m is a positive integer; and

time tARA does not exceed m * (k-1) * (tOE), wherein;

tARA is measured from the time that an address of a location is made available to said memory to the time when one or more of said sense amplifiers develop an output signal indicative of the contents of said location; and

tOE is the time to transfer an output of any one of said sense amplifiers to said output of said memory.

5. The memory of claim 1

wherein, in burst mode, a time in which each location of said plurality except said one of said locations is read out to said output after a previous location has been read out to said output is shorter than a time in which said one of said locations is read out to said output after said address of said one of said locations has been received by said memory.

6. The memory of claim 1 wherein said memory is fabricated in an integrated circuit.

7. The memory of claim 1 further comprising:

a plurality of second registers, each second register for receiving at least a portion of a column address; and

a circuitry for each second register for selecting in response to signals from one of the second registers a plurality of columns to be read by the sense amplifiers.

10. The memory of claim 7 wherein:

said set of locations comprises k subsets S-1, . . . , S-k wherein k is greater than or equal to two, such that, for a positive integer m and for any subset S-i, the contents of m consecutively addressed locations from said subset S-i can be transferred simultaneously to said plurality of sense amplifier circuits; and

in said operation, time tARA does not exceed m * (k-1) * (tOE), wherein;

tARA is measured from the time that an address of the first location to be read out in said operation is made available to said memory to the time when said plurality of sense amplifier circuits develops an output signal indicative of the contents of said first location; and

tOE is the time to transfer the contents of any one of said locations from said plurality of sense amplifier circuits to said output.

13. The memory of claim 7 wherein in said operation any number of said locations addressed consecutively with wrap around can be read out to said output so that:

the first location to be read out in said operation is read out to said output after time tARA+tOE wherein;

tARA is measured from the time that an address of said first location is made available to said memory to the time when said plurality of sense amplifier circuits develops an output signal indicative of the contents of said first location; and

tOE is the time to transfer the contents of any one of said locations from said plurality of sense amplifier circuits to said output of said memory; and

every other location to be read out in said operation is read out to said output within time tOE.

8. A memory comprising:

a set of consecutively addressed memory locations L1, . . . Ln;

a plurality of sense amplifier circuits for amplifying contents of said memory locations; and

an output for providing output signals from said plurality of sense amplifier circuits,

wherein said memory has a burst mode operation for receiving an address and reading out to said output, in response to said address, any given number of memory locations in the sequence of consecutive addresses with wrap around so that the next location, if any, to be read out after said location Ln is said location L1, such that during said operation while the contents of any location L to be read out other than the last location to be read out are being transferred from said plurality of sense amplifier circuits to said output, the contents of another location to be read out after said location L are being provided to said plurality of sense amplifier circuits for amplification and subsequent transfer to said output, and

wherein said memory further comprises a control circuit for selectively enabling said sense amplifier circuits so that said control circuit enables a sense amplifier circuit whose output signals are being transferred to the output of said memory but said control circuit does not enable all said sense amplifier circuits at the same time.

9. The memory of claim 8 wherein, during said operation, said control circuit enables at the same time only:

(1) the sense amplifier circuit whose output signals are being transferred to said output of said memory, and

(2) a predetermined number of other sense amplifier circuits whose output signals will be transferred next to said output of said memory if said operation continues sufficiently long.

11. The memory of claim 8 wherein, in said operation, each location to be read out except the first location to be read out is read out to said output in a shorter time than the first location to be read out.

12. The memory of claim 8 wherein the sequence of locations L1, . . . , Ln is a sequence of increasing order of addresses.

14. The memory of claim 8 wherein said memory is fabricated in an integrated circuit.

15. In a memory having a plurality of rows of memory locations and having a plurality of row decoders and one X-register for each said row decoder, a method of reading in a burst mode operation a plurality of consecutively addressed memory locations spanning more than one row, said method comprising the steps of:

providing to said X-registers a row address of a first location to be read in said burst mode operation;

for each row containing a location to be read in said burst mode operation, performing the steps of;

providing by at least one of the X-registers to at least one of the row decoders signals identifying said row;

activating by one of said row decoders at least a portion of said row;

sensing and amplifying contents of at least one location of said row; and

transferring amplified contents of at least one location of said row to an output of said memory;

wherein for at least two locations L1 and L2 of said plurality which are in different rows having different row addresses in said memory, the step of sensing and amplifying the contents of said location L2 overlaps in time with the step of transferring the amplified contents of said location L1 to said output of said memory.

16. The method of claim 15 wherein:

said memory comprises a plurality of sense amplifier circuits, and each sensing and amplifying step is performed by at least one of said sense amplifier circuits; and

for at least two locations LL1 and LL2 of said plurality, during the step of transferring the amplified contents of said location LL1 to said output the sense amplifier circuit for sensing and amplifying the contents of said location LL1 is enabled and the sense amplifier circuit for sensing and amplifying the contents of said location LL2 is disabled, but said sense amplifier circuit for sensing and amplifying the contents of said location LL2 is enabled subsequently during the step of sensing and amplifying the contents of said location LL2.

17. The method of claim 15, further comprising the steps of:

providing at least a portion of a column address of the first location to be read in said operation to at least one of Y-registers of said memory; and

providing, by at least one of the Y registers, signals identifying a plurality of columns of the memory such that memory locations in said plurality of columns in one row have consecutive addresses,

wherein the sensing and amplifying step comprises the step of sensing and amplifying contents of memory locations in said plurality of columns.

18. The method of claim 17 wherein the transferring step comprises the step of transferring the amplified contents to the output consecutively in the sequence of addresses.

19. In a memory comprising a set of consecutively addressed memory locations L1, . . . , Ln, and a plurality of sense amplifier circuits, a method of reading out in burst mode a sequence of locations addressed consecutively with wrap around so that the next location to be read out after location Ln is location L1, said method comprising the steps of:

receiving an address of a first location to be read out in burst mode; and

in response to said address, for each location of said sequence performing the steps;

sensing and amplifying contents of said location; and

transferring amplified contents of said location to an output of said memory,

wherein for any location L of said sequence other than the last location to be read out in said sequence, the transferring step for the location L overlaps in time with the sensing and amplifying step for another location to be read out after said location L in said sequence; and

for at least one location LL of said sequence, before the sensing and amplifying step for said location LL, the sense amplifier circuit which is to perform the sensing and amplifying step for the location LL is enabled, and after the transferring step for location LL, the sense amplifier circuit that has performed the sensing and amplifying step for location LL is disabled, and another sense amplifier circuit which is to perform the sensing and amplifying step for another location to be read out in said sequence is enabled.

20. An integrated memory comprising:

an array of memory locations, the array comprising a plurality of subarrays, each subarray comprising a predetermined number of groups of columns of the memory locations such that for any given column position in a group, the memory locations in any given row in the columns at said given position in the groups of the subarray have consecutive addresses;

one X-decoder for each subarray;

one X-register for each X-decoder;

one Y-decoder for each subarray;

one Y-register for each Y-decoder;

one Y-select circuit for each subarray, the Y-select circuit being responsive to the Y-decoder of the subarray to select all the columns that occupy a selected position in the groups of the subarray;

a plurality of sense amplifier circuits for each subarray, each sense amplifier circuit for amplifying signals from a column selected by the Y-select circuit of the subarray;

a memory output; and

a control circuit for selecting one of the sense amplifier circuits to provide data to the memory output,

wherein in a burst mode read operation, at least one X-register provides to its respective X-decoder signals identifying a row in one of the subarrays, and at least one Y-register provides to its respective Y-decoder signals identifying a position of columns in the groups of one of the subarrays.

21. The memory of claim 20 wherein said subarrays are two in number.

22. The memory of claim 20 wherein in the burst mode read operation while data from the sense amplifier circuits of one of the subarrays are provided to the memory output, the sense amplifier circuits of another one of the subarrays develop output signals corresponding to data in said other one of the subarrays.

23. The memory of claim 20 wherein in the burst mode read operation, the control circuit enables the sense amplifier circuit selected to provide data to the memory output and at the same time disables one or more sense amplifier circuits not selected to provide data to the memory output.