Apparatus and method for protecting data in a memory address range

• US 5,559,992 A
• Filed: 01/11/1993
• Issued: 09/24/1996
• Est. Priority Date: 01/11/1993
• Status: Expired due to Term

• Current Assignee: Ascom Autelca, Ltd
• Original Assignee: Ascom Autelca AG (Ascom Holding AG)
• Inventors: Fl uckiger, Daniel, Stutz, Peter
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/002,737
• Time in Patent Office: 1,352 Days
• Field of Search: 395/425, 395/490, 395/185.03, 395/185.04, 371/57.1, 371/60, 371/21.1, 365/195, 365/72, 365/205, 327/202, 327/218, 364/464.02
• US Class Current: 711/163
• CPC Class Codes: G06F 12/1441 for a range

Abstract

A data protection apparatus has chip select logic, a protection circuit and one or more memory devices. The chip select logic is designed so that when protected memory is addressed, more than one selection signal is generated. In this way, a protected memory area may encompass all, or a portion, of one or more memory devices. The additional selection signal is processed by a protection circuit which will interrupt the processor if protected memory is addressed during a write cycle in the absence of a request signal which the processor is programmed to generate just prior to its writing to a protected memory area.

Claims

1. A data protection apparatus comprising:

a processor addressing an address space, a memory area comprising a first memory, a bus interconnecting the processor and said first memory, a first address decoder generating a first selection signal in response to addresses in a first range of said first memory selected by the processor;

a second address decoder generating a second selection signal in response to addresses in a second range of addresses of said first memory selected by the processor, said second range of addresses being nonidentical to the first range of addresses and having at least one address in common with the first range; and

a protection circuit operatively coupled to the processor to receive a request signal therefrom, said protection circuit annunciating the event of generation of a second selection signal in the absence of receipt of a request signal.

2. The data protection apparatus of claim 1 further characterized in that the first address decoder generates a plurality of selection signals such that for each of a multiplicity of addresses in the address space, exactly one of the plurality of selection signals is generated.

3. The data protection apparatus of claim 1 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

4. The data protection apparatus of claim 1 wherein the first address decoder, second address decoder and protection circuit comprise an application-specific integrated circuit.

5. The data protection apparatus of claim 4 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

6. The data protection apparatus of claim 1 further comprising a second memory in said memory area, wherein the first address decoder generates a third selection signal in response to addresses in a third range of addresses in said memory area, the third range having no addresses in common with the first range, the third range having at least one address in common with the second range, and wherein said second memory is selected by the third selection signal.

7. The data protection apparatus of claim 6 wherein the first address decoder, second address decoder and protection circuit comprise an application-specific integrated circuit.

8. The data protection apparatus of claim 6 wherein the first and second memories are nonvolatile, and employ differing storage technologies.

9. The data protection apparatus of claim 8 further comprising postage printing means controlled by the processor and first and second descending registers indicative of an amount of postage available for printing;

wherein the first descending register is stored in the first memory within the second range of addresses, and the second descending register is stored in the second memory within the second range of addresses, whereby data contained in the descending register are protected from spurious processor write cycles.

10. The data protection apparatus of claim 8 wherein the first address decoder, second address decoder and protection circuit comprise an application-specific integrated circuit.

11. The data protection apparatus of claim 10 further comprising postage printing means controlled by the processor and first and second descending registers indicative of an amount of postage available for printing;

wherein the first descending register is stored in the first memory within the second range of addresses, and the second descending register is stored in the second memory within the second range of addresses, whereby data contained in the descending register are protected from spurious processor write cycles.

12. The data protection apparatus of claim 1 further comprising a third address decoder responding to an address in said memory area, and wherein the request signal received by the protection circuit comprises a read cycle for the address.

13. The data protection apparatus of claim 12 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

14. The data protection apparatus of claim 12 wherein the first address decoder, second address decoder, third address decoder and protection circuit comprise an application-specific integrated circuit.

15. The data protection apparatus of claim 14 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

16. The data protection apparatus of claim 12 further comprising a second memory in said memory area, wherein the first address decoder generates a third selection signal in response to addresses in a third range of addresses in said memory area, the third range having no addresses in common with the first range, the third range having at least one address in common with the second range, and wherein said second memory is selected by the third selection signal.

17. The data protection apparatus of claim 16 wherein the first and second memories are nonvolatile, and employ differing storage technologies.

18. The data protection apparatus of claim 17 further comprising postage printing means controlled by the processor and first and second descending registers indicative of an amount of postage available for printing;

wherein the first descending register is stored in the first memory within the second range of addresses, and the second descending register is stored in the second memory within the second range of addresses, whereby data contained in the descending register are protected from spurious processor write cycles.

19. The data protection apparatus of claim 12 wherein the protection circuit comprises first and second bistable gates, the first bistable gate being set to a first state by the request signal and set to a second state by a write cycle in the absence of the request signal, said write cycle includes issuing a write signal, the second bistable gate receiving a clocked input signal from the first bistable gate, said input signal being an output signal of the first bistable gate, the second bistable gate being clocked during the write cycle by a trigger signal derived from the write signal, said trigger signal indicating the processor'"'"'s addressing an address in the second range, the output of the second bistable gate comprising the annunciation.

20. The data protection apparatus of claim 19 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

21. The data protection apparatus of claim 19 wherein the first and second bistable gates comprise D-type flip-flops each having a clock input terminal, a D input terminal, a set input terminal and an output terminal, the write signal operatively connected to the clock input terminal of the first gate, the D input terminal of the first gate operatively connected to a logic "low" level, the set input terminal of the first gate operatively connected to the request signal, the clock input terminal of the second gate receiving the conjunction of the write signal and the second selection signal, the D input terminal of the second gate receiving an output signal of the first gate, and an output signal of the second gate comprising the annunciation.

22. The data protection apparatus of claim 21 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

23. The data protection apparatus of claim 1 wherein the processor has a nonmaskable interrupt input terminal, and wherein the protection circuit annunciates the event by generating a nonmaskable interrupt input signal.

24. The data protection apparatus of claim 23 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

25. The data protection apparatus of claim 23 wherein the first address decoder, second address decoder and protection circuit comprise an application-specific integrated circuit.

26. The data protection apparatus of claim 25 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

27. The data protection apparatus of claim 23 further comprising a third address decoder responding to an address in said memory area, and wherein the request signal received by the protection circuit comprises a read cycle for the address.

28. The data protection apparatus of claim 27 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

29. The data protection apparatus of claim 23 further comprising a second memory in said memory area, wherein the first address decoder generates a third selection signal in response to addresses in a third range of addresses in said memory area, the third range having no addresses in common with the first range, the third range having at least one address in common with the second range, and wherein said second memory is selected by the third selection signal.

30. The data protection apparatus of claim 29 wherein the first and second memories are nonvolatile, and employ differing storage technologies.

31. The data protection apparatus of claim 30 further comprising postage printing means controlled by the processor and first and second descending registers indicative of an amount of postage available for printing;

wherein the first descending register is stored in the first memory within the second range of addresses, and the second descending register is stored in the second memory within the second range of addresses, whereby data contained in the descending register are protected from spurious processor write cycles.

32. The data protection apparatus of claim 2 wherein the protection circuit comprises first and second bistable gates, the first bistable gate being set to a first state by the request signal and set to a second state by a write cycle in the absence of the request signal, said write cycle includes issuing a write signal, the second bistable gate receiving a clocked input signal from the first bistable gate, said input signal being an output signal of the first bistable gate, the second bistable gate being clocked during the write cycle by a trigger signal derived from the write signal, said trigger signal indicating the processor'"'"'s addressing an address in the second range, the output of the second bistable gate comprising the annunciation.

33. The data protection apparatus of claim 32 further comprising postage printing means controlled by the processor and a descending register comprising data indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby the descending register data are protected from spurious processor write cycles.

34. The data protection apparatus of claim 32 wherein the first and second bistable gates comprise D-type flip-flops each having a clock input terminal, a D input terminal, a set input terminal and an output terminal, the write signal operatively connected to the clock input terminal of the first gate, the D input terminal of the first gate operatively connected to a logic "low" level, the set input terminal of the first gate operatively connected to the request signal, the clock input terminal of the second gate receiving the conjunction of the write signal and the second selection signal, the D input terminal of the second gate receiving an output signal of the first gate, and an output signal of the second gate comprising the annunciation.

35. The data protection apparatus of claim 34 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

36. The data protection apparatus of claim 1 wherein the protection circuit comprises first and second bistable gates, the first bistable gate being set to a first state by the request signal and set to a second state by a write cycle in the absence of the request signal, said write cycle includes issuing a write signal, the second bistable gate receiving a clocked input signal from the first bistable gate, said input signal being an output signal of the first bistable gate, the second bistable gate being clocked during the write cycle by a trigger signal derived from the write signal, said trigger signal indicating the processor'"'"'s addressing an address in the second range, the output of the second bistable gate comprising the annunciation.

37. The data protection apparatus of claim 36 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

38. The data protection apparatus of claim 36 wherein the first address decoder, second address decoder, protection circuit, first bistable gate and second bistable gate comprise an application-specific integrated circuit.

39. The data protection apparatus of claim 38 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

40. The data protection apparatus of claim 36 wherein the first and second bistable gates comprise D-type flip-flops each having a clock input terminal, a D input terminal, a set input terminal and an output terminal, the write signal operatively connected to the clock input terminal of the first gate, the D input terminal of the first gate operatively connected to a logic "low" level, the set input terminal of the first gate operatively connected to the request signal, the clock input terminal of the second gate receiving the conjunction of the write signal and the second selection signal, the D input terminal of the second gate receiving an output signal of the first gate, and an output signal of the second gate comprising the annunciation.

41. The data protection apparatus of claim 40 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

42. The data protection apparatus of claim 40 wherein the first address decoder, second address decoder, protection circuit, first bistable gate and second bistable gate comprise an application-specific integrated circuit.

43. The data protection apparatus of claim 42 further comprising postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and the descending register is stored in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

44. The data protection apparatus of claim 36 further comprising a second memory in said memory area, wherein the first address decoder generates a third selection signal in response to addresses in a third range of addresses in said memory area, the third range having no addresses in common with the first range, the third range having at least one address in common with the second range, and wherein said second memory is selected by the third selection signal.

45. The data protection apparatus of claim 44 wherein the first and second bistable gates comprise D-type flip-flops each having a clock input terminal, a D input terminal, a set input terminal and an output terminal, the write signal operatively connected to the clock input terminal of the first gate, the D input terminal of the first gate operatively connected to a logic "low" levels, the set input terminal of the first gate operatively connected to the request signal, the clock input terminal of the second gate receiving the conjunction of the write signal and the second selection signal, the D input terminal of the second gate receiving an output signal of the first gate, and an output signal of the second gate comprising the annunciation.

46. The data protection apparatus of claim 44 wherein the first and second memories are nonvolatile, and employ differing storage technologies.

47. The data protection apparatus of claim 46 further comprising postage printing means controlled by the processor and first and second descending registers indicative of an amount of postage available for printing;

wherein the first descending register is stored in the first memory within the second range of addresses, and the second descending register is stored in the second memory within the second range of addresses, whereby data contained in the descending register are protected from spurious processor write cycles.

48. The data protection apparatus of claim 46 wherein the first and second bistable gates comprise D-type flip-flops each having a clock input terminal, a D input terminal, a set input terminal and an output terminal, the write signal operatively connected to the clock input terminal of the first gate, the D input terminal of the first gate operatively connected to a logic "low" level, the set input terminal of the first gate operatively connected to the request signal, the clock input terminal of the second gate receiving the conjunction of the write signal and the second selection signal, the D input terminal of the second gate receiving an output signal of the first gate, and an output signal of the second gate comprising the annunciation.

49. The data protection apparatus of claim 48 further comprising postage printing means controlled by the processor and first and second descending registers indicative of an amount of postage available for printing;

wherein the first descending register is stored in the first memory within the second range of addresses, and the second descending register is stored in the second memory within the second range of addresses, whereby data contained in the descending register are protected from spurious processor write cycles.

50. A method for use with a data protection apparatus comprising a processor addressing an address space, a first memory, a bus interconnecting the processor and said first memory, a first address decoder generating a first selection signal in response to addresses in a first range of said first memory selected by the processor, a second address decoder generating a second selection signal in response to addresses in a second range of addresses of said first memory selected by the processor, said second range of addresses being nonidentical to the first range of addresses and having at least one address in common with the first range, and a protection circuit operatively coupled to the processor to receive a request signal therefrom, the method comprising the steps of:

addressing an address in the second range of addresses;

generating the second selection signal in the second address decoder; and

annunciating in the protection circuit whether the second selection signal has been generated in the absence of receipt of a request signal.

51. The method of claim 50 wherein the protection circuit of the apparatus comprises first and second bistable gates, and wherein the method comprises, after the generating step and before the annunciating step, the further steps of:

clocking the first bistable gate to a first state;

receiving an output signal of the first bistable gate in the first state at the second bistable gate; and

clocking the second bistable gate, an output signal of the second bistable gate comprising an annunciation.

52. The method of claim 50 wherein the apparatus further comprises postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing, and wherein the first memory is nonvolatile, the method comprising the additional step of:

in the event of generation of the second selection signal after the receipt of the request signal, storing the descending register in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

53. The method of claim 50 wherein the apparatus further comprises a third address decoder responding to a predetermined address, and wherein the request signal comprises a read cycle for the predetermined address, and wherein the annunciating step further comprises annunciating in the protection circuit whether the second selection signal has been generated in the absence of receipt of the read cycle for the predetermined address.

54. The method of claim 53 wherein the apparatus further comprises postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing, and wherein the first memory is nonvolatile, the method comprising the additional step of:

in the event of generation of the second selection signal after the receipt of the read cycle for the predetermined address, storing the descending register in the first memory within the second range of addresses;

whereby data contained in the descending register are protected from spurious processor write cycles.

55. The method of claim 50 wherein the processor has a nonmaskable interrupt input terminal, and wherein the method comprises, after the step of annunciating in the protection circuit, the further step of:

annunciating to the processor the event of generation of the second selection signal in the absence of receipt of a request signal by generating a nonmaskable interrupt input signal.

56. The method of claim 55 wherein the apparatus further comprises postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing, and wherein the first memory is nonvolatile, the method comprising, before the addressing step, the additional step of:

storing the descending register in the first memory within the second range of addresses,

whereby data contained in the descending register are protected from spurious processor write cycles.

57. The method of claim 55 wherein the apparatus further comprises a third address decoder responding to a predetermined address, and wherein the request signal comprises a read cycle for the predetermined address, and wherein the method further comprises, after the step of generating the second selection signal and before the step of annunciating in the protection circuit whether the second selection signal has been generated in the absence of receipt of a request signal, annunciating in the protection circuit the event of generation of the second selection signal in the absence of receipt of the read cycle for the predetermined address.

58. The method of claim 57 wherein the apparatus further comprises postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, the method comprising, before the addressing step, the additional step of;

storing the descending register in the first memory within the second range of addresses,

whereby data contained in the descending register are protected from spurious processor write cycles.

59. A method for protecting a memory region, said method for use with a data protection apparatus comprising a processor addressing an address space, at least one memory area comprising a first memory, a bus interconnecting the processor and said first memory, a first address decoder generating a first selection signal in response to addresses in a first range of said first memory selected by the processor, a second address decoder generating a second selection signal in response to addresses in a second range of addresses of said first memory selected by the processor, said second range of addresses being nonidentical to the first range of addresses and having at least one address in common with the first range, and a protection circuit operatively coupled to the processor to receive a request signal therefrom, the method comprising the steps of:

generating a request signal;

addressing an address in the second range of addresses during a write cycle;

generating the second selection signal in the second address decoder;

annunciating, by said protection circuit, the event of generation of the second selection signal in the absence of receipt of the request signal;

and writing to an address in the second range of addresses only in the absence of the protection circuit annunciation.

60. The method of claim 59 for use with the data protection apparatus, wherein the protection circuit of the apparatus comprises first and second bistable gates, said method further comprising, after the first generating step and before the addressing step, a step of setting the first bistable gate to a first state, and, after the second generating step and before the writing step, a step of clocking the second bistable gate.

61. The method of claim 59 wherein the apparatus further comprises a third address decoder responding to a predetermined address in said at least one memory area, and wherein the request signal comprises a read cycle for the predetermined address.

62. The method of claim 59 wherein the apparatus further comprises postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile; and

wherein the step of writing to an address in the second range of addresses comprises storing the descending register within the second range of addresses, whereby data contained in the descending register are protected from spurious processor write cycles.

63. The method of claim 61 wherein the apparatus further comprises postage printing means controlled by the processor and a descending register indicative of an amount of postage available for printing;

and wherein the first memory is nonvolatile, and wherein the step of writing to an address in the second range of addresses comprises storing the descending register within the second range of addresses, whereby data contained in the descending register are protected from spurious processor write cycles.

64. A method for use with a data protection apparatus comprising a processor, a memory device, a protection circuit operatively coupled to the processor to receive a request signal therefrom, and an address decoder generating a selection signal corresponding to a protected region of the memory device, the protected region comprising less than all of the addresses of the memory device, the method comprising the steps of:

addressing an address in the protected region of the memory device during a write cycle;

providing an output signal annunciating whether the request signal has been received by the protection circuit prior to the addressing step; and

interrupting the processor if no request signal has been received prior to the addressing step.