Programmable, multi-purpose virtual pin multiplier

• US 5,561,773 A
• Filed: 04/30/1993
• Issued: 10/01/1996
• Est. Priority Date: 04/30/1993
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Barajas, Saul, Whittaker, Bruce E., Kalish, David M.
• Primary Examiner(s): Hayes, Gail O.
• Assistant Examiner(s): Ives, Felicia
• Application Number:
  US08/056,324
• Time in Patent Office: 1,250 Days
• Field of Search: 371/22.2, 326/39, 326/40, 326/41, 326/45, 395/275, 395/700, 364/926
• US Class Current: 710/104
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22

Abstract

A system and circuitry is provided by which certain selected embedded pins of an integrated circuit gate array may be provided with dual functions, that is to say, they may act either as receivers of an externally sourced input signal or as transmitters of an internally generated output signal. Each selected input/output pin is controlled by an associated flip-flop residing in a chain of flip-flops so that an associated flip-flop will determine the condition of two buffer-drivers attached to each input/output pin. While the first buffer-driver is tri-stated (disabled), then the embedded pin operates as an input receiving function. When the first buffer-driver is enabled, the embedded I/O pin operates as the conveyer of an output signal from the internal output logic.

Claims

1. In an application specific integrated circuit gate array chip having multiple I/O pins for connection to outside circuitry, a method of enabling a selected plurality of I/O pins to be immediately programmed by external maintenance means on each initialization cycle, for either receiving external signals as input to said chip or for sending external logic signals out of said chip to said outside circuitry, said method comprising the steps of:

(a) setting the on-off state of each one of a series of flip-flops where each flip-flop is associated with a single I/O pin to set the high impedance/low impedance condition of a pair of buffer-drivers connected to each one of said I/O pins;

(b) enabling a first one of said pair of buffer-drivers, associated with each one of said selected I/O pins, to transmit internal logic signals out through said I/O pin;

(c) preventing, said transmitted logic signals out, from re-entering said gate array chip;

(d) disabling said first one of said pair of buffer-drivers and enabling said second one of said buffer-drivers to permit an externally sourced input signal from said I/O pin into said application specific integrated circuit gate array chip.

2. A network in an application specific integrated circuit gate array chip for enabling a selected plurality of an unlimited number of terminal pins to function either as a receiver of external sourced input signals or as a transmitter of internal logic output signals and wherein an external maintenance logic means operates to immediately program each one of a plurality of flip-flops where each flip-flop is associated with a first and second set of buffer-drivers controlling the signal direction capability of each selected terminal pin, comprising:

(a) said plurality of flip-flops having settable on-off state conditions settable by said external maintenance logic means wherein each flip-flop controls a particular one of an associated buffer-driver means;

(b) said selected plurality of an unlimited number terminal pins being settable to function as a receiver or transmitter of signals as controlled by said associated buffer-driver means;

(c) each said buffer-driver means including;

(c1) a first buffer-driver for enabling said internal logic output signals to be transmitted from said chip via said terminal pin to an external element when turned on by an enabling signal from said associated flip-flop;

(c2) a second buffer-driver for enabling said terminal pin to receive said externally sourced input signals when said first buffer-driver is disabled and including an output signal to a gating input means;

(c3) said gating input means to receive the said output signal of said second buffer-driver and transmit the said external sourced input signal to internal gate array logic when said first buffer-driver is disabled;

(d) means, when said first buffer-driver is enabled, for blocking said logic output signals from re-entering said gate array chip;

(e) a shift register including said plurality of flip-flops;

(f) said external maintenance logic means for setting each of said flip-flops into a predetermined on-off state;

(g) wherein each selected one of said plurality of flip-flops is set to either enable its associated first buffer-driver to pass internally generated logic signals to said terminal pin for external transmission output while disabling said second buffer-driver, or to disable said first buffer-driver and enable said second buffer-driver to pass externally sourced input signals into said chip.

3. The network of claim 2 wherein said first buffer-driver includes:

(a) means to receive a signal reflecting said predetermined state of its associated flip-flop for setting said first buffer-driver into a low impedance condition or a high impedance condition.

4. The network of claim 2 wherein said gating input means includes:

(a) means, sensitive to said signal reflecting said predetermined state of its associated flip-flop, for disabling/enabling the connection of input signals from said second buffer-driver to internal input logic in said chip.

5. A system for enabling each I/O pin of an unlimited multiplicity of I/O pins in an application specific integrated circuit gate array chip to function as either a receiver of input signals or transmitter of output signals comprising:

(a) means for enabling an internally generated output logic signal onto said I/O pin for external transmission while disabling said I/O pin'"'"'s connection to internal logic in said chip;

(b) means for disabling said internally generated output logic signal from said I/O pin and enabling internal input logic to receive an externally sourced input signal;

(c) control means for immediately activating said means for enabling or said means for disabling including;

(c1) a plurality of flip-flops forming a chained sequence where each flip-flop is settable to either a "1" or "0" state by programming from an external maintenance means and each one of a plurality of said I/O pins is associated with a specific flip-flop which enables/disables its associated I/O pin as either an output transmitting terminal or an input receiving terminal.

6. Apparatus for virtually multiplying the usable number of I/O pins in an application specific integrated circuit gate array chip without physically adding additional I/O pins and permitting instant reprogrammability of the input or output function of each I/O pin during each new initialization cycle set up by a maintenance control means, said apparatus comprising:

(a) a selected plurality of I/O pins functioning as contact for either input signals to be received by said chip or as contact for output signals to be transmitted from said chip;

(b) a plurality of buffer-driver means associated with each I/O pin for connecting internally sourced output signals to said I/O pins for external transmission to external circuitry or alternatively, connecting externally sourced input signals into said chip;

(c) flip-flop means, programmable on each said initialization cycle, for setting each one of said plurality of buffer-driver means into an output mode or input mode;

(d) said maintenance control means, operating during each new initialization cycle, for instantly shifting in programming signals to each one of said buffer driver means;

(e) means for disabling connection from a selected I/O pin to internal input logic in said chip during output mode periods when said selected I/O pin is enabled for connection to internal output logic generated signals for transmission of said generated signals to said external circuitry.