Method and apparatus to improve read reliability in semiconductor memories

• US 5,566,194 A
• Filed: 06/06/1995
• Issued: 10/15/1996
• Est. Priority Date: 10/30/1992
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven, Mielke, Neal
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/471,139
• Time in Patent Office: 497 Days
• Field of Search: 371/81.1
• US Class Current: 714/805
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error in data read from an memory array, apparatus for providing a first value to determine a wait period, apparatus responsive to the detection of an error for providing a second value, apparatus responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.

Claims

1. An apparatus for controlling a period during which control circuitry of a memory array waits before latching output data comprising:

means for detecting, based on the output data, the presence of an error in the output data;

means for providing a first value to determine a wait period;

means responsive to the detection of an error for providing a second value; and

means responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.

2. A method for improving read reliability in a memory array comprising the steps of:

(a) initiating a read operation from the memory array;

(b) latching data provided by the read operation after a first predetermined period;

(c) checking the data provided by the read operation to determine whether the data contains an error; and

(d) repeating the step of initiating the read operation from the memory array if the data provided by the read operation contains an error, and latching data after a second predetermined period, wherein the second predetermined period is longer than the first predetermined period.

3. The method of claim 2, further comprising the step of repeating the step of initiating the read operation at a next address.

4. The method of claim 2, further comprising the step of continually repeating the steps of initiating the read operation and latching data after continually longer predetermined periods until the data provided by the read operation is error-free.

5. The method of claim 2, wherein the memory array is a flash EEPROM array.

6. An apparatus for reading data from a memory array, the apparatus comprising:

a data latch which latches data from the memory array after a first period;

an error detection circuit coupled to the data latch for determining, based on the data latched from the memory array, whether the data latched from the memory array contains an error; and

a control circuit coupled to the data latch and the error detection circuit which, if the error detection circuit determines the data latched from the memory array contains an error, indicates to the data latch to latch data from the memory array after a second period.

7. The apparatus of claim 6, wherein the second period is longer than the first period.

8. The apparatus of claim 6, wherein the control circuit continually repeats indicating to the data latch to latch data from the memory array after continually longer periods until the data latched from the memory array is error-free.

9. The apparatus of claim 6, further comprising data selection logic, coupled to the control circuit, for transferring an address for a read operation to the memory array.

10. The apparatus of claim 6, wherein the memory array is a flash EEPROM array.

11. A memory system comprising:

a memory array;

a lookup table including a plurality of logical sector numbers and a plurality of physical position indicators of the memory array which correspond to the plurality of logical sector numbers; and

a control circuit coupled to the memory array and the lookup table which determines a physical position in the memory array of an address, wherein the control circuit transfers the physical position for a read operation to the memory array and latches data provided by the read operation after a first period, wherein the control circuit also checks the data latched from the memory array to determine whether the data contains an error, and wherein the control circuit repeats, provided the data latched does contain an error, the transfer of the physical position for the read operation to the memory array and latches data provided by the read operation after a second period, the second period being longer than the first period.

12. The system of claim 11, wherein the memory array comprises an array of Flash EEPROM memory.