Method and apparatus for assigning and analyzing timing specifications in a computer aided engineering program
First Claim
1. A method for applying timing specifications in a logic design, wherein the logic design includes logic design inputs, logic design outputs and a plurality of logic elements coupled together to form at least one path from a logic design input to one or more logic design outputs via the plurality of logic elements, wherein a logic element includes at least one logic element input and at least one logic element output for coupling to other logic elements, the logic design inputs and the logic design outputs, wherein each logic element, logic element input, logic element output, logic design input and logic design output comprises a node, wherein one or more nodes exist on the paths, the method executing on a computer system operated by a human user, the computer system including a processor coupled to a user input device and an output device, the method comprising the steps of:
- (a) inputting a timing specification by a user using the user input device, wherein the timing specification comprises a timing parameter assigned to a first user-selected node in a path;
(b) using the processor to identify a path that originates at a logic design input, passes through the first node, and terminates at a logic design output;
(c) using the processor to determine a timing property of an electrical signal transmitted through the identified path, wherein the timing property corresponds with the timing parameter;
(d) using the processor to compare the timing property of the identified path with the timing parameter; and
(e) using the output device to indicate the relationship of the identified path'"'"'s timing property to the timing parameter.
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Abstract
A system for allowing a user to assign timing specifications to points in a circuit and have the timing properties of the circuit analyzed with respect to the timing specifications. The system allows timing specifications such as maximum propagation delay, clock-to-output delay, setup time and maximum clock frequency to be assigned at any point in the circuit. The system uses predefined rules to determine which of multiple possible specifications are to be used in analyzing each path of the circuit. A method of concurrently performing the assignment and analysis is described.
88 Citations
9 Claims
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1. A method for applying timing specifications in a logic design, wherein the logic design includes logic design inputs, logic design outputs and a plurality of logic elements coupled together to form at least one path from a logic design input to one or more logic design outputs via the plurality of logic elements, wherein a logic element includes at least one logic element input and at least one logic element output for coupling to other logic elements, the logic design inputs and the logic design outputs, wherein each logic element, logic element input, logic element output, logic design input and logic design output comprises a node, wherein one or more nodes exist on the paths, the method executing on a computer system operated by a human user, the computer system including a processor coupled to a user input device and an output device, the method comprising the steps of:
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(a) inputting a timing specification by a user using the user input device, wherein the timing specification comprises a timing parameter assigned to a first user-selected node in a path; (b) using the processor to identify a path that originates at a logic design input, passes through the first node, and terminates at a logic design output; (c) using the processor to determine a timing property of an electrical signal transmitted through the identified path, wherein the timing property corresponds with the timing parameter; (d) using the processor to compare the timing property of the identified path with the timing parameter; and (e) using the output device to indicate the relationship of the identified path'"'"'s timing property to the timing parameter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus for processing timing specifications in a logic design, the apparatus comprising:
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a computer system coupled to a user input device, an output device and a processor; a logic design description included within the computer system, wherein the logic design description includes logic design inputs, logic design outputs and a plurality of logic elements wherein a logic element includes at least one logic element input and at least one logic element output for coupling to other logic elements, the logic design inputs and the logic design outputs, wherein each logic element, logic element input, logic element output, logic design input and logic design output comprises a node, wherein one or more nodes exist on the paths; defining means for accepting signals from the user input device by a user to define a timing specification, comprising a timing parameter associated with a first node in a path; identification means coupled to the processor for identifying a path that originates at a logic design input, passes through the first node, and terminates at a logic design output; determining means coupled to the processor for determining a timing property of an electrical signal transmitted through the identified path, wherein the timing property is associated with the timing specification; comparing means coupled to the processor for comparing the timing property of the identified path with the timing specification; and indicating means coupled to the processor and the output device for outputing the relationship between the identified path'"'"'s timing property and the timing specification.
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Specification