Single-polysilicon CMOS active pixel

• US 5,576,763 A
• Filed: 11/22/1994
• Issued: 11/19/1996
• Est. Priority Date: 11/22/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Ackland, Bryan D., Dickinson, Alexander G., Inglis, David A., Eid, El-Sayed I.
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): Ho, Tuan V.
• Application Number:
  US08/344,785
• Time in Patent Office: 728 Days
• Field of Search: 348/294, 348/302, 348/303, 348/307, 348/308, 348/311, 348/313
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 31/1136 the device being a metal-insulator-semiconductor field-effect transistor

Abstract

The single-polysilicon active pixel comprises a photo site located on a substrate for generating and storing charge carriers, the charge carriers being generated from photonic energy incident upon the photo site and semiconductor substrate, a photo gate, a transfer transistor and output and reset electronics. The gate of the transfer transistor and the photo gate are defined in a single layer of polysilicon disposed on the semiconductor substrate. The source of transfer transistor is a doped region of substrate, referred to as a coupling diffusion, which provides the electrical coupling between the photo gate and the transfer transistor. The coupling diffusion allows for the transfer of a signal stored in a photo site under the photo gate to the output electronics for processing. The single-polysilicon active pixel may be operated by biasing the transfer transistor to the low operating voltage of the pixel, for example, 0 volts. By virtue of the structure of the single-polysilicon active pixel, this mode of operation results in the same timing as if the transfer transistor were clocked, but neither a clock nor the associated driving circuitry are required. However, there is little no tendency for image lag as occurs in double polysilicon active pixels when they are operated in a manner which avoids clocking the transfer gate.

Claims

1. A single polysilicon CMOS active pixel for converting an optical signal to an electronic signal by applying a first collection voltage and a second transfer voltage, comprising:

a semiconductor substrate wherein charge carriers are generated from incident photonic energy;

a photo gate and a transfer transistor gate defined in a single layer of polysilicon disposed on the semiconductor substrate, the photo gate having a first and a second state wherein in the first state the first collection voltage is applied to the photo gate that causes the charge carriers to be stored in a first region within the semiconductor substrate beneath the photo gate, the stored charge carriers defining a signal, and in the second state the second transfer voltage is applied which results in movement of the charge carriers from the first region;

a transfer transistor comprising the transfer transistor gate, a first diffusion region and a second diffusion region, wherein the first diffusion region is located between the photo gate and the transfer transistor gate and functions as a source of the transfer transistor, and wherein the second diffusion region functions as a drain of the transfer transistor, the second diffusion region having a first potential and a second potential, wherein the second potential is a predetermined fixed value based on the first collection voltage and the first potential is a function of the second potential and the signal;

output electronics, electrically connected to the second diffusion region, which receives the signal from the second diffusion region and conducts the signal to processing electronics; and

reset electronics to reset the second diffusion region to the second potential;

wherein in the first state of the transfer transistor, the transfer transistor is inactive so that the signal remains in the first region and in the second state the transfer transistor is active so that the signal flows from the first region to the first diffusion and to the output electronics.

2. The single polysilicon CMOS active pixel of claim 1 wherein the single polysilicon CMOS active pixel has an N-channel configuration.

3. The single polysilicon CMOS active pixel of claim 1 wherein the first state of the photo gate is an integration period.

4. The single polysilicon CMOS active pixel of claim 1 wherein the first voltage is 5 volts.

5. The single polysilicon CMOS active pixel of claim 1 wherein the second voltage is 0 volts.

6. The single polysilicon CMOS active pixel of claim 1 wherein the second potential is 5 volts minus a voltage drop across the reset electronics.

7. The single polysilicon CMOS active pixel of claim 1 wherein the output electronics comprise a voltage follower transistor electrically connected to a select transistor, wherein the voltage follower transistor is electrically connected to the second diffusion.

8. The single polysilicon CMOS active pixel of claim 1 wherein the reset electronics comprises a reset transistor electrically connected to the second diffusion.

9. The single polysilicon CMOS active pixel of claim 1 wherein the first region is a photo site.

10. A method for operating a single-polysilicon CMOS n-channel active pixel having a photo gate, a clock, and a transfer transistor which has a transfer transistor gate and a diffusion node, the single-polysilicon CMOS active pixel operable by a first voltage and a second voltage, comprising the steps of:

(a) biasing the transfer transistor to the second voltage;

(b) clocking the photo gate to the first voltage, the first voltage on the photo gate being maintained until a first desired period of time has elapsed, wherein a signal is stored in a first region during the first desired period of time;

(c) resetting the diffusion node to a third voltage based on the first voltage;

(d) clocking the photo gate to the second voltage when the first desired period of time has elapsed, and maintaining the second voltage until a second desired period of time has elapsed, wherein, during the second desired period of time, the signal is transferred out of the first region to the diffusion node changing the third voltage on the diffusion node; and

(e) repeating steps (b)-(d).

11. The method of claim 10 wherein the single polysilicon active pixel is n-channel.

12. The method of claim 10 wherein the first voltage has a higher potential than the second voltage.

13. The method of claim 10 wherein the first voltage is 5 volts and the second voltage is 0 volts.

14. The method of claim 10 wherein the second voltage is 0 volts.

15. The method of claim 10 wherein the first desired period of time is about 30 milliseconds.

16. The method of claim 10 wherein the step of resetting the diffusion node comprises activating a reset transistor, which reset transistor has a drain biased to the first voltage and has a source electrically connected to the diffusion node.