Integrated content addressable read only memory

• US 5,576,985 A
• Filed: 03/25/1996
• Issued: 11/19/1996
• Est. Priority Date: 03/25/1996
• Status: Expired due to Term

• Current Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Original Assignee: Klaus Holtz
• Inventors: Holtz, Klaus
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/620,908
• Time in Patent Office: 239 Days
• Field of Search: 365/49, 365/190, 365/189.01, 365/185.01, 365/94, 365/96, 365/105, 365/255.7
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/046 using non-volatile storage elements

Abstract

An integrated memory device can be used as a Content Addressable Memory (CAM) or as a Random Addressable Memory (RAM) for applications in data compression, video compression or Autosophy robots. Memory addressing employs long chains of Field Effect Transistors, forming a logical AND function, and programmable non volatile connection cells which can be implemented either as programmable fuses or memory transistors including PROM, EPROM, EEPROM or FLUSH technologies. Each connection cell is programmable for either connection or non connection. Each chain of Field Effect Transistors may generate any arbitrary output address code which is programmed via diodes and the same non volatile connection cells used to decode the input data words. The device combines extreme low power consumption with very fast search access speed. Devices implemented as flexible thin foils can be folded into very large, compact and robust memory arrays.

Claims

1. In a data processing system an integrated content or random addressable read only memory device in which a plurality of binary input data patterns, received by an input station, are converted into binary output address codes, on an output station, where each unique binary input data pattern results in a binary output address code, comprising:

means including at least two driver circuits for accepting the binary input data pattern from the input station and generating a true output signal and a false output signal for each binary bit, respectively, in the binary input data pattern through each driver circuit each generating an inverting or false and a non inverting or true output signal;

means defining a multiple line selection grid using rows and columns;

means for applying the true and the false output signals from each of the driver circuits to the columns of said multiple line selection grid;

means defining an array of logical and gates by serial rows of field effect transistors, each field effect transistor representing an input to the logical and gate;

means defining connection cells programmable for either connection or non connection;

means for connecting either the true or the false output signal from each driver output on the grid to said array of logical and gates via said connection cells so that each logical and gate is connected to a unique binary input data pattern;

means defining a diode function;

means for generating said binary output address code, when the unique binary input data pattern is applied, from the output of each logical and gate in the array via said diode function and said connection cells;

means for directing the resulting binary output address code to an output station.

2. A device as set forth in claim 1, where said connection cells are programmed during the device layout, through hard wired connections, according to a list of pre-assembled input data patterns.

3. A device as set forth in claim 1, where said connection cells are programmed during the manufacturing process, by setting internal fuses, according to a list of pre-assembled input data patterns.

4. A device as set forth in claim 3 where said fuses are set by mechanical indentations or pits in the device surface.

5. A device as set forth in claim 3 where said fuses are set by depositing conductive materials through holes in the device surface.

6. A device as set forth in claim 3 where said fuses are burned out on the device surface by an external laser beam.

7. A device as set forth in claim 3 where said fuses are blown out through a secondary fuse selection grid and the application of programming voltage pulses.

8. A device as set forth in claim 3 where said fuses are implemented as antifuses which are set through a secondary antifuse selection grid and the application of programming voltage pulses.

9. A device as set forth in claim 1, where said connection cells are implemented as memory transistors which are programmed by depositing electical charges into the chip substrate during the device operations using a secondary memory transistor selection grid and programming voltage pulses.