Method and apparatus for configurable build-in self-repairing of ASIC memories design

• US 5,577,050 A
• Filed: 12/28/1994
• Issued: 11/19/1996
• Est. Priority Date: 12/28/1994
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Li, Charles, Zarrinfar, Farzad, Kablanian, Adam, Bair, Owen S.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/365,286
• Time in Patent Office: 692 Days
• Field of Search: 371/10.1, 371/10.2, 371/10.3, 371/11.1, 365/200, 365/201
• US Class Current: 714/710
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

A logic circuit and a technique for repairing faulty memory cells internally by employing on-chip testing and repairing circuits in an ASIC system. The test circuit detects column line faults, row faults, and data retention faults in a memory array. The repair circuit redirects the original address locations of the faulty memory lines to the mapped address locations of the redundant column or row lines. This repair scheme includes redundant column lines attached to each of the I/O arrays in the memory array and redundant row lines to replace detected memory faults. These testing and repairing procedures are performed within the chip without the aid of any external equipment.

Claims

1. A method for on-chip testing and repairing configurable ASIC memories in a system that contains a test circuit, a repair circuit, a memory array, and a plurality of redundant lines within the memory array, the method comprising the steps of:

testing the memory array;

determining an original address of a line in the memory array that includes a fault; and

repairing the faulty line with a redundant line by using the repair circuit to redirect the original address to an address of the redundant line.

2. The method according to claim 1, further comprising the step of:

prior to the repairing step, translating the original address to the redundant line address.

3. The method according to claim 2, further comprising the step of:

prior to the translating step, storing the original address.

4. The method according to claim 3, further comprising the step of:

prior to the storing step, transferring the original address from the test circuit to the repair circuit.

5. The method according to claim 1, wherein the redirecting step further comprises the steps of:

redirecting an original address of a faulty column to a redundant column line address; and

redirecting an original address of a faulty row to a redundant row line address.

6. The method according to claim 2, wherein the translation step further comprises the steps of:

translating an original address of a faulty column to a redundant column line address; and

translating an original address of a faulty row to a redundant row line address.

7. The method according to claim 3, wherein the storing step further comprises the steps of:

storing an original address for a faulty column; and

storing an original address for a faulty row.

8. The method according to claim 4, wherein the transferring step further comprises the steps of:

transferring an original address of a faulty column to a redundant column line; and

transferring an original address of a faulty row to a redundant row line.

9. The method according to claim 1, further comprising the steps of:

generating a first test pattern using a test pattern generator to detect a column fault in the memory array, including a stuck-at, a stuck-open, and a bridging fault; and

generating a second test pattern using the test pattern generator to detect a row fault in the memory array, including a data retention fault within a memory cell.

10. The method according to claim 9, further comprising the steps of:

using the test circuit to detect an address of a column line in the memory array which includes a fault; and

using the test circuit to detect an address of a row line in the memory array which includes a fault.

17. The method of claim 1, wherein the repairing step comprises:

redirecting the original address to the address of the redundant line by using a line address correction circuit to reconfigure the mapping of input addresses to the physical space of the memory array.

11. A process for on-chip testing and repairing configurable ASIC memories in a system that contains a test circuit, a repair circuit, a memory array, and a plurality of redundant lines within the memory array, the test circuit including a test pattern generator, the process comprising the steps of:

supplying a test pattern by the test pattern generator for testing a plurality of memory cells in the memory array;

detecting at least one fault in the memory array by the test circuit;

transferring the original address location of the at least one faulty line from the test circuit to the repair circuit;

storing an original address location of the at least one faulty memory line;

translating the original address location of the at least one faulty line to a mapped address location of at least one redundant line; and

redirecting the original address location of the at least one faulty line to the mapped address location of the at least one redundant line.

12. The process according to claim 11 wherein the redirecting step further comprises the steps of:

redirecting the original address location of the at least one faulty column to the mapped address location of the at least one redundant column line by the repair circuit; and

redirecting the original address location of the at least one faulty row to the mapped address location of the at least one redundant row line by the repair circuit.

13. An on-chip system for testing and repairing faulty ASIC memories comprising:

a memory array including a matrix of memory cells formed by intersecting a plurality of column lines with a plurality of row lines;

a redundant line, coupled to the memory array, for replacing faulty lines;

a testing circuit, coupled to the memory array, for testing the memory array and determining an original address of a line in the memory array that includes a fault; and

a repair circuit, coupled to the memory array and the testing circuit, for repairing the faulty line with a redundant line by redirecting the original address to an address of the redundant line.

14. The system according to claim 13 wherein the repair circuit comprises:

a line fault signature circuit, for storing the original address of a line in the memory array that includes a fault; and

,

a line address correction circuit, for redirecting the original address to an address of the redundant line by reconfiguring the mapping of input addresses to the physical space of the memory array.

15. The system according to claim 13, further comprising:

a redundant column line, coupled to the memory array, for replacing faulty columns in the memory array; and

,

a redundant row line, coupled to the memory array, for replacing faulty rows in the memory array.

16. The system according to claim 15, wherein the repair circuit comprises:

a column self repair circuit, including a column fault signature circuit and a column address correction circuit, for storing the original address of a column in the memory array that includes a fault and for redirecting the original address to an address of a redundant column by reconfiguring the mapping of input addresses to the physical space of the memory array; and

a row self repair circuit, including a row fault signature circuit and a row address correction circuit, for storing the original address of a row in the memory array that includes a fault and for redirecting the original address to an address of a redundant row by reconfiguring the mapping of input addresses to the physical space of the memory array.