Storage access authorization controls in a computer system using dynamic translation of large addresses

• US 5,577,231 A
• Filed: 12/06/1994
• Issued: 11/19/1996
• Est. Priority Date: 12/06/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Starke, William J., Scalzi, Casper A.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US08/349,771
• Time in Patent Office: 714 Days
• Field of Search: 364/200, 395/500, 395/800, 395/375, 395/400, 395/650, 395/416
• US Class Current: 703/26
• CPC Class Codes: G06F 9/45537 Provision of facilities of other operating environments, e.g. WINE I/O emulation G06F13/105

Abstract

A method of using the DAT mechanism in a computer processor to extend both: 1) the native storage access authorization architecture of the processor, and 2) to enable the processor to execute programs designed to operate under different storage access architectures. An executing program (called a source program) uses "source effective addresses" (source EAs) for locating its instructions and storage operands while executing on the processor (called the target processor).

Claims

1. A method of extending access authority controls in a processor having dynamic address translation (DAT), comprising the following steps for:

generating a source effective address (EA) for accessing data in a source page in a source storage of an executing source program on the processor, the source EA having fewer bits than a target VEA provided to a DAT mechanism in the processor for dynamic address translation,

also generating access authority codes (AAC) for identifying particular access authority constraints for an access by a source EA to a source page frame in source real storage, the source page frame being located in a target page frame in a target real storage of the processor,

writing the AACs in bits of the target VEA not written into by the source EA for generating the target VEA as a combination of the source EA and the AACs, the bits containing the AACs forming AAC fields respectively containing the access authority codes, the target VEA addressing a target virtual page in target virtual storage,

transferring the target VEA to the DAT mechanism, and locating by the DAT mechanism of any valid target page table entry (target PTE) containing an address to a target page frame assigned to the target VEA by a previous translation of the target VEA, and accessing the target page frame to obtain data required by the source VEA, but

signalling a target page fault by the DAT mechanism if no valid target PTE is found for the target VEA, then

decoding the AACs in the target VEA to determine if any AAC prevents completion of the storage access for the source VEA if no valid target PTE is found for the target VEA, and terminating the access if any AAC prevents completion of the storage access, but if no AAC prevents completion of the storage access, then

address translating the target VEA by assigning a page table entry and a target page frame in the target real storage to the target VEA, writing a page frame real address to the target page frame in the target PTE and writing a validation indication in the target PTE to enable it to represent an access with particular access authority constraints for the source page frame in the source virtual storage.

2. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 1, further comprising processor steps for:

writing a synonym set of one or more target PTEs each translating to the same target page frame, and the target PTEs in the same synonym set respectively associated with different target virtual addresses having different values in their AAC fields representing accesses with different access authority states.

3. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 2, further comprising processor steps for:

setting up a synonym association area and a page frame synonym directory in target virtual storage, the synonym association area containing one synonym pointer entry for each target PTE in the target page table, and the page frame directory containing one directory pointer entry for representing one source page frame in the target real storage, and

locating by each directory pointer entry of a synonym set of synonym pointer entries in the synonym association area respectively representing a corresponding set of synonym target PTEs for the same source page frame.

4. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 3, further comprising a processor step for:

storing a pointer in each directory pointer entry for addressing a first synonym pointer entry in the set associated with the source page frame represented by the directory pointer entry.

5. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 4, further comprising a processor step for:

storing a pointer in each synonym pointer entry for addressing a next synonym pointer entry in the set associated with the source page frame represented by the directory pointer entry.

6. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 1, in and unique AAC fields whose processing includes the steps of:

before executing a source program, determining each access authority code for the source program which will not change during execution of the source program, and

storing a corresponding non-changeable AAC value recognizable by the target system for each non-changeable AAC found by the determining step, and

storing each non-changeable value for preparation of the target VEAs during execution of the source program.

7. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 6, further comprising the steps of:

including in the determining step a determination of any storage key as a non-changeable AAC to be used in the execution of the source program, and

storing a storage key value, corresponding to a storage key determined by the determining step, in a respective AAC field assigned to receive a storage key constraint value in each target VEA when the target VEA is being generated in the execution of the source program.

8. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 6, further comprising the steps of:

including in the determining step a determination of any address space identifier (ASID) as a non-changeable AAC to be used in a later execution of the source program, and

storing an ASID value, corresponding to the ASID determined by the determining step, in a respective AAC field assigned to receive an ASID constraint value for the non-changeable AAC in each target VEA when the target VEA is being generated in the execution of the source program.

9. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 6, further comprising the steps of:

including in the determining step a determination that DAT is not being used by the source program, and assigning a non-DAT address space identifier (no-DAT ASID) for use as a non-changeable AAC to be used in a later execution of the source program, and

storing a non-DAT ASID value, corresponding to the non-DAT determination by the determining step, in a respective AAC field assigned in each target VEA to receive an ASID constraint value for the non-changeable AAC when the target VEA is being generated in the execution of the source program.

10. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 1, further comprising the steps of:

determining each changeable AAC during each storage access request, the changeable AAC being changeable for each access during execution by the source program on the target processor, and

storing a changeable AAC value corresponding to the changeable AAC for the storage access request in an AAC field reserved for the changeable AAC in the target VEA being generated for the storage access request by the source program.

11. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 10, further comprising the steps of:

determining the changeable AAC as being a fetch AAC or store AAC upon each storage access requested by the source program during execution on the target processor, and

storing a changeable AAC value corresponding to the fetch AAC or store AAC in an AAC field reserved for the changeable AAC in the target VEA being generated for the storage access request.

12. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 1, further comprising the steps of:

before executing a source program, determining any AAC needed for execution of the source program for which the AAC will not change during execution of the source program,

storing a non-changeable AAC value, corresponding to the AAC code, recognizable by the target system for each non-changeable AAC found by the determining step,

storing each non-changeable value in the target system for later use during execution of the source program when generating the target VEAs,

when executing the source program, determining each changeable AAC during each storage access request, the changeable AAC being changeable upon each access during execution by the source program on the target processor, and

in a target VEA being generated for each source storage access request, storing in AAC fields reserved for different types of source storage requests the changeable and non-changeable AAC values required for the storage access.

13. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 12, further comprising the steps of:

detecting by a DAT mechanism in the target processor for existence of a prior address translation for each generated target VEA, and

indicating validity of the target VEA if the prior address translation is found, and

if validity is found, using the prior address translation of the target VEA without detecting any AAC value to allow fast accessing of data in the target page frame indicated by the address translation.

14. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 13, further comprising the steps of:

detecting by the DAT mechanism in the target processor for existence of a prior address translation for each generated target VEA, and

if no prior address translation for the VEA is found, performing the validation of all source access authority control settings in the target VEA, in accordance with source machine architecture rules, and

if the access is valid under source access control rules, establishing a PTE to allow the access, and

if the access is not valid, communicating the source machine exception to the source program using the architecture specification of the source machine to report the exception.

15. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 14, further comprising the steps of:

inserting a base field in each target VEA, the base field containing a target virtual address for locating the start of a source storage area in the target processor'"'"'s virtual storage.

16. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 15, further comprising the steps of:

dividing the target processor'"'"'s virtual storage into a plurality of source spaces, in which each source space includes at least one type of each different permutation of useable values of all AAC fields in the target VEA.

17. A method of extending access authority controls in a target processor having dynamic address translation (DAT) as defined in claim 15, further comprising the steps of:

dividing part of the target processor'"'"'s virtual storage into plural versions of a source address space, in which the plural versions each comprise plural representations of the same source address space and a plurality of different permutation of useable values of all AAC fields, the versions including;

a resolved version for mapping to real storage space previously accessed units of the source virtual address space and its AAC permutations, an unresolved version not mapping to real storage space previously defined units of the source virtual address space and its AAC permutations, and a third real address version of the target virtual address space representing real source address space for containing source program data obtained by using real source addresses.

18. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 17, further comprising the steps of:

changing a unique source address space identifier (ASID) for each source address space to the resolved version from the unresolved version for which the source program specifies a virtual address, the determining step locating a target translation table for mapping units of the source virtual address space into units of target real storage to resolve a representation of the source ASID in the target translation table, and

assigning another representation in the target translation table for source real addresses in the real address version not having a source ASID and not having any source virtual address space.

19. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 18, further comprising the steps of:

executing the source program with;

     1) resolved source ASIDs in the resolved version, and

     2) token representations of source ASIDs being resolved by the changing step, and

     3) source real addresses not having any ASID or token representation of any source ASID, the resolved and unresolved source ASIDs having assigned sets of contiguous storage unit entries in the target translation table to the source ASID,

dynamically resolving any token representation of a source ASID by assignment of a set of contiguous storage unit entries in the target translation table, and

assigning a set of contiguous storage unit entries in the target translation table to source real storage units of any source real storage needed to execute the source program.

20. A method of extending access authority controls in a processor having dynamic address translation (DAT) as defined in claim 19, further comprising the steps of:

assigning different contiguous parts of the target translation table to the same source storage unit having different combinations of access states and the same ASID, and

also assigning a different contiguous part of the target translation table to the real address version for representing any source real storage needed to execute the source program.