Semiconductor memory cell having information storage transistor and switching transistor

• US 5,581,106 A
• Filed: 10/11/1995
• Issued: 12/03/1996
• Est. Priority Date: 12/10/1992
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Matsushita, Takeshi, Hayashi, Yutaka
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/541,180
• Time in Patent Office: 419 Days
• Field of Search: 257/365, 257/366, 257/369, 257/401
• US Class Current: 257/369
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR₁ comprising a semiconductor channel layer Ch₁, first and second conductive gates G₁, G₂, and first and second conductive layers L₁, L₂ ; and a switching transistor TR₂ comprising a semiconductor channel forming region Ch₂, a third conductive gate G₃, and third and fourth conductive layers L₃, L₄, wherein the fourth conductive layer L₄ is connected to the second conductive gate G₂, the first conductive gate G₁ and the third conductive gate G₃ are connected to a first memory-cell-selection line, the first conductive layer L₁ and the third conductive layer L₃ are connected to a second memory-cell-selection line, the second conductive layer L₂ is connected to a fixed potential, and the semiconductor channel forming region Ch₂ is connected to a read/write selection line.

Claims

1. A semiconductor memory cell comprising:

an information storage transistor of a first conductivity type, comprising a first semiconductor channel forming region having a first principal surface;

first and second conductive regions each forming a rectifier junction in contacting relationship with a surface region of said first semiconductor channel forming region; and

a first conductive gate disposed opposite said first principal surface, with a first barrier layer interposed therebetween, in such a manner as to bridge said first conductive region and said second conductive region, and

a switching transistor of a second conductivity type opposite to the first conductivity type, comprising a second semiconductor channel forming region having second and third opposing principal surfaces;

third and fourth conductive regions respectively connected to either end of said second semiconductor channel forming region; and

a second conductive gate disposed opposite said second principal surface with a second barrier layer interposed therebetween, wherein

said first conductive gate of said information storage transistor and said second conductive gate of said switching transistor are connected to a first memory-cell-selection line;

said fourth conductive region of said switching transistor is connected to said semiconductor channel forming region of said information storage transistor;

said third conductive region of said switching transistor is connected to a second memory-cell-selection line,

said second conductive region of said information storage transistor is connected to a fixed potential, and

said first conductive region of said information storage transistor is connected to said third conductive region of said switching transistor, forming a rectifier junction therebetween.

2. A semiconductor memory cell according to claim 1, further comprising a third conductive gate disposed opposite said third principal surface of said second semiconductor channel forming region with a third barrier layer interposed therebetween.