Power level detection circuit

• US 5,581,206 A
• Filed: 07/28/1995
• Issued: 12/03/1996
• Est. Priority Date: 07/28/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Quantum Devices Inc (Micron Technology, Inc.)
• Inventors: Roohparvar, Frankie F., Chevallier, Christophe J., Briner, Michael S.
• Primary Examiner(s): Tran, Toan
• Application Number:
  US08/509,021
• Time in Patent Office: 494 Days
• Field of Search: 327/142, 327/143, 327/198, 327/72, 327/77-81, 327/87, 327/88, 327/89, 327/530, 327/538, 327/543, 327/545, 327/546, 327/227, 327/228, 327/229, 327/230
• US Class Current: 327/143
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output. The amplified comparator output functions to hold the system elements in a reset state at very low supply voltages and the one shot output functions to reset the system elements once the supply voltage is at a sufficiently high level.

Claims

1. A level detection circuit for producing a detection output when an input signal reaches a predetermined level, said detection circuit including:

voltage reference circuit means for producing a reference voltage having a magnitude which is relatively independent of the input signal magnitude at least once the input signal has reached a first operating voltage;

translator circuit means for producing a translated voltage having a magnitude which is indicative of the magnitude of the input signal;

comparator means for comparing the reference voltage and the translated voltage and for producing a comparator output based upon the comparison, with the comparator means being powered by the input signal; and

outputting means for producing the detection output signal in response to the comparator output, with the outputting means including one shot means for producing an output pulse having a duration greater than a predetermined minimum duration in response to the comparator output and logical combining means for causing the detection output signal to be produced when either the output pulse or the comparator output are present.

2. The level detection circuit of claim 1 wherein the voltage reference circuit means is powered by the input signal and where the logical combining means includes an OR gate circuit.

3. The level detection circuit of claim 2 wherein the translator circuit means is powered by the input signal and wherein the output pulse and the comparator output are positive-going signals relative to a circuit common.

4. The level detection circuit of claim 1 wherein the reference voltage produced by the voltage reference circuit means is derived from the threshold voltage of an MOS transistor.

5. The level detection circuit of claim 4 wherein the MOS transistor of the voltage reference circuit means is a P channel transistor.

6. The level detection circuit of claim 5 wherein the reference voltage is approximately equal to the threshold voltage of the transistor and said first operating voltage is equal to the threshold voltage.

7. The level detection circuit of claim 4 wherein the MOS transistor of the voltage reference circuit means has its gate and drain connected together and the reference voltage is equal to the gate-source voltage of the MOS transistor.

8. The level detection circuit of claim 7 wherein the voltage reference circuit means includes a resistor connected in series with the MOS transistor.

9. The level detection circuit of claim 8 wherein the resistor is connected intermediate the MOS transistor and a node where the input signal is applied to the voltage reference circuit.

10. The level detection circuit of claim 9 further including a capacitor coupled between a junction of the MOS transistor and the resistor and a circuit common.

11. The level detection circuit of claim 4 wherein the comparator means includes a first and second differentially-connected P channel transistors, with the first P channel transistor having a gate which receives the reference voltage and the second P channel transistor having a gate which receives the translated voltage.

12. The level detection circuit of claim 11 wherein the comparator means includes a pair of N channel transistors connected with respect to the first and second P channel transistors to form a current mirror load.

13. The level detection circuit of claim 1 wherein the comparator means changes from a first state to a second state when the input signal is at a first level and from the second state to the first state when the input signal is at a second level and the level detection circuit further includes feedback means for generating a feedback signal in response to the comparator output which causes the second level to differ from the first level.

14. The level detection circuit of claim 13 wherein the input voltage is a positive voltage with respect to a circuit common and wherein the feedback means causes the input signal second level to be at a voltage different than the input signal at the first level.

15. The level detection circuit of claim 14 wherein the translator circuit means includes a first N channel transistor having its drain-source connected between the input signal and a translator circuit means output where the translated voltage is produced.

16. The level detection circuit of claim 15 wherein the translator circuit means includes a resistor connected between the translator circuit means output and a circuit common.

17. The level detection circuit of claim 16 wherein the translator circuit means includes a capacitor coupled between the translator circuit means output and the circuit common.

18. The level detection circuit of claim 15 further including feedback means for altering the magnitude of the translated voltage in response to the comparator output.

19. The level detection circuit of claim 18 wherein the feedback means includes a second N channel transistor having a drain and source connected in parallel with the drain and source of the first N channel transistor and a gate signal having a magnitude which varies with the comparator output.

20. The level detection circuit of claim 1 wherein the level detection circuit is switchable between an enabled mode of operation and a disabled mode of operation in response to an enable signal and wherein the translated voltage of the translator circuit means differs from the input signal voltage by the drain-source voltage of an MOS transistor and wherein the MOS transistor switches between a conductive and a non-conductive state in response to the enable signal.

21. The level detection circuit of claim 1 wherein the voltage reference circuit means, the translator circuit means, the comparator means and the outputting means are formed in a common integrated circuit.

22. A level detection circuit for producing an detection output when an input signal reaches a predetermined level, said detection circuit including:

voltage reference circuit means for producing a reference voltage having a magnitude which is relatively independent of the input signal magnitude at least once the input signal has reached a first operating voltage;

translator circuit means for producing a translated voltage having a magnitude which is indicative of the magnitude of the input signal, with the translator circuit means being powered by the input signal;

comparator means for comparing the reference voltage and the translated voltage and for producing a comparator output based upon the comparison, with the comparator output changing from a first state to a second state based upon relative magnitudes of the reference voltage and translated voltage, with the comparator means being powered by the input signal; and

outputting means for producing the detection output signal in response to the comparator output, with the outputting means being powered by the input signal and with the outputting means producing a first component of the output signal prior to the comparator output changing from the first state to the second state which is indicative of the input signal magnitude and producing a second component of the output signal in a form of a pulse having a duration greater than a predetermined minimum duration subsequent to the comparator output changing from the first state to the second state.

23. The level detection circuit of claim 22 wherein the voltage reference circuit means is powered by the input signal and the reference voltage is derived from the threshold voltage of a first MOS transistor and wherein the translated voltage differs from the input signal voltage by the drain-source voltage of a second MOS transistor.

24. The level detection circuit of claim 23 wherein the first MOS transistor is a P channel transistor and the second MOS transistor is an N channel transistor and the comparator means included a pair of differentially-connected P channel MOS transistors having their gates connected to receive the translated voltage and the reference voltage, respectively.

25. The level detection circuit of claim 24 wherein the comparator means includes a pair of N channel transistors connected with respect to the pair of P channel transistors so as to form a current mirror load.

26. The level detection circuit of claim 25 wherein the level detection circuit is switchable between an enabled mode of operation and a disabled mode of operation in response to an enable signal and wherein the second MOS transistor of the translator circuit means switches between a conductive state and a non-conductive state in response to the enable signal.

27. The level detection circuit of claim 26 wherein the voltage reference circuit means includes a first enable transistor having its drain and source connected in series with the drain and source of the first MOS transistor, with the first enable transistor switching between a conductive state and a non-conductive state in response to the enable signal.

28. The level detection circuit of claim 27 wherein the comparator means includes a second enable transistor connected in parallel with one of the N channel load transistors, with the second enable transistor switching between a conductive and a non-conductive state in response to the enable signal.

29. The level detection circuit of claim 22 wherein the reference is derived from the threshold voltage of an MOS transistor and wherein the MOS transistor has a body and a source coupled together.

30. The level detection circuit of claim 29 wherein the MOS transistor is a P channel transistor formed in an N type well, with the N type well being the MOS transistor body.

31. A level detection circuit for producing an detection output when an input signal reaches a predetermined level, said detection circuit including:

voltage reference circuit means for producing a reference voltage having a magnitude which is relatively independent of the input signal magnitude at least once the input signal has reached a first operating voltage, with the reference voltage being equal to the gate-source voltage an MOS transistor having a gate and drain connected together, with the voltage reference circuit means including a resistor connected in series with the MOS transistor, intermediate the MOS transistor and a node where the input signal is applied, and a capacitor coupled between a junction of the resistor and the MOS transistor and a circuit common;

translator circuit means for producing a translated voltage having a magnitude which is indicative of the magnitude of the input signal;

comparator means for comparing the reference voltage and the translated voltage and for producing a comparator output based upon the comparison, with the comparator means being powered by the input signal; and

outputting means for producing the detection output signal in response to the comparator output.

32. A level detection circuit for producing a detection output when an input signal reaches a predetermined level, said detection circuit including:

voltage reference circuit means for producing a reference voltage having a magnitude which is relatively independent of the input signal magnitude at least once the input signal has reached a first operating voltage;

translator circuit means for producing a translated voltage having a magnitude which is indicative of the magnitude of the input signal and including a first N channel transistor having its drain-source connected between the input signal and a translator circuit means output where the translated voltage is produced and including a resistor connected between the translator circuit means output and a circuit common and a capacitor coupled between the translator circuit means output and the circuit common;

comparator means for comparing the reference voltage and the translated voltage and for producing a comparator output based upon the comparison, with the comparator means being powered by the input signal and with the comparator means changes from a first state to a second when the input is at a first level and from the second state to the first state when the input is at the second level;

outputting means for producing the detection output signal in response to the comparator output; and

feedback means for generating a feedback signal in response to the comparator output which causes the first level to differ from the second level and wherein the input voltage is a positive voltage with respect to the circuit common and the feedback means causes the input signal second level to be at a voltage different than the input signal at the first level.

33. A level detection circuit for producing a detection output when an input signal reaches a predetermined level, said detection circuit being switchable between an enabled mode and a disabled mode of operation in response to an enable signal and including:

voltage reference circuit means for producing a reference voltage having a magnitude which is relatively independent of the input signal magnitude at least once the input signal has reached a first operating voltage;

translator circuit means for producing a translated voltage having a magnitude which is indicative of the magnitude of the input signal, with the translator circuit means including an MOS transistor connected such that the translated voltage differs from the input signal voltage by the drain-source voltage of the MOS transistor and wherein the MOS transistor switches between a conductive and non-conductive state in response to the enable signal;

comparator means for comparing the reference voltage and the translated voltage and for producing a comparator output based upon the comparison, with the comparator means being powered by the input signal; and

outputting means for producing the detection output signal in response to the comparator output.

34. A level detection circuit for producing an detection output when an input signal reaches a predetermined level, said detection circuit being switchable between an enabled mode of operation and a disabled mode of operation in response to an enable signal and including:

voltage reference circuit means for producing a reference voltage having a magnitude which is relatively independent of the input signal magnitude at least once the input signal has reached a first operating voltage, with the voltage reference circuit being powered by the input signal and including a first P channel MOS transistor, with the reference voltage being derived from a threshold voltage of the first MOS transistor;

translator circuit means for producing a translated voltage having a magnitude which is indicative of the magnitude of the input signal, with the translator circuit means being powered by the input signal and including a second N channel MOS transistor and wherein the translated voltage differs from the input signal voltage by the drain-source voltage of the second MOS transistor, with the second MOS transistor switches between a conductive state and a non-conductive state in response to the enable signal;

comparator means for comparing the reference voltage and the translated voltage and for producing a comparator output based upon the comparison, with the comparator means being powered by the input signal, with the comparator means including a pair of differentially-connected P channel MOS transistors having their gates connected to receive the translated voltage and the reference voltage, respectively and a pair of pair of N channel MOS transistors connected with respect to the pair of P channel transistors so as to form a current mirror load; and

outputting means for producing the detection output signal in response to the comparator output, with the outputting means being powered by the input signal.

35. The level detection circuit of claim 34 wherein the voltage reference circuit means includes a first enable MOS transistor having its drain and source connected in series with the drain and source of the first MOS transistor, with the first enable transistor switching between a conductive state and a non-conductive state in response to the enable signal.

36. The level detection circuit of claim 35 wherein the comparator means includes a second enable MOS transistor connected in parallel with one of the N channel load transistors, with the second enable transistor switching between a conductive and a non-conductive state in response to the enable signal.