Method of making a bipolar stripe transistor structure

• US 5,591,651 A
• Filed: 07/12/1995
• Issued: 01/07/1997
• Est. Priority Date: 07/15/1994
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Chen, Yaw-Hwang
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/501,757
• Time in Patent Office: 545 Days
• Field of Search: 437/31, 437/33, 437/69
• US Class Current: 438/362
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/732 Vertical transistors

Abstract

This invention pertains to a lateral bipolar transistor comprising an emitter, a base and a collector. The transistor exhibits improved function and overall size reduction, due to the base and emitter structure. An island forms both the base and emitter regions in the transistor structure with the base region being above the collector region, below the emitter region, and surrounded by a dielectric region. The emitter is surrounded by emitter isolation walls, which are formed approximately 0.2 microns above the plane of the dielectric region, such that any manufacturing variances will not cause the emitter isolation walls to contact the dielectric region and pinch-off the base region from the base junction region. This structure also allows the size of the base-emitter junction to be decreased without increasing the parasitic characteristics of the transistor.

Claims

1. A method of manufacturing a transistor on a substrate comprising the steps of:

a) forming a collector on said substrate, said collector having a collector mesa region, a sub-collector channel region below said collector mesa region and a collector contact region adjacent to and isolated from said collector mesa region;

b) forming a base region in said collector mesa region;

c) forming a field oxide region having an upper surface and a lower surface on said sub-collector channel region, said field oxide region substantially surrounding said collector mesa region, said lower surface of said field oxide region being on said sub-collector channel region, said upper surface of said field oxide region extending above the junction between said collector mesa region and said base region;

d) forming an emitter region on said base region, said emitter region being smaller in diameter than said base region;

e) forming emitter isolation walls having an upper surface and a lower surface around said emitter region, said lower surface of said emitter isolation walls extending into said base region, said lower surface of said emitter isolation walls does not extend down into said base region far enough to intersect the plane of said upper surface of said field oxide region;

f) forming a base polysilicon layer, a collector polysilicon layer and an emitter polysilicon layer on said base region, said collector region and said emitter region, respectively, and

g) forming a base contact pad, a collector contact pad and an emitter contact pad on said base polysilicon layer, said collector polysilicon layer and said emitter polysilicon layer, respectively.

2. The method of manufacturing a transistor according to claim 1 wherein said field oxide region is formed approximately 2000 angstroms below an upper surface of said base region.

3. The method of manufacturing a transistor according to claim 2 wherein said emitter isolation walls are extended approximately 1000 angstroms into said upper surface of said base region.

4. The method of manufacturing a transistor according to claim 3 wherein said base region is approximately 0.9 microns in diameter.