Process of manufacturing a microelectric device using a removable support substrate and etch-stop

• US 5,591,678 A
• Filed: 06/07/1995
• Issued: 01/07/1997
• Est. Priority Date: 01/19/1993
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: HE Holdings, Inc. (Rtx Corporation)
• Inventors: Bendik, Joseph J., Finnila, Ronald M., Malloy, Gerard T.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US08/482,172
• Time in Patent Office: 580 Days
• Field of Search: 437/208, 437/974, 437/915, 148/DIG. 135, 148/DIG. 150, 156/630, 156/662, 156/901
• US Class Current: 438/459
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: Y10S 148/135 Removal of substrate
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A microelectronic device is fabricated by furnishing a first substrate (40) having a silicon etchable layer (42), a silicon dioxide etch-stop layer (44) overlying the silicon layer (42), and a single-crystal silicon wafer (46) overlying the etch-stop layer (44), the wafer (46) having a front surface (52) not contacting the etch stop layer (44). A microelectronic circuit element (50) is formed in the single-crystal silicon wafer (46). The method further includes attaching the front surface (52) of the single-crystal silicon wafer (46) to a second substrate (58), and etching away the silicon layer (42) of the first substrate (40) down to the etch-stop layer (44). The second substrate (58) may also have a microelectronic circuit element (58'"'"') therein that can be electrically interconnected to the microelectronic circuit element (50).

Claims

1. A method of fabricating a microelectronic device, comprising the steps of:

furnishing a first substrate having an etchable layer, an etch-stop layer overlying the etchable layer, and a wafer overlying the etch-stop layer;

forming a microelectronic circuit element in the exposed side of the wafer of the first substrate opposite to the side overlying the etch-stop layer;

attaching the wafer of the first substrate to a second substrate; and

etching away the etchable layer of the first substrate down to the etch-stop layer.

2. The method of claim 1, further including an additional step, after the step of etching, of

patterning the etch-stop layer.

3. The method of claim 2, further including an additional step, after the step of patterning, of

forming an electrical connection to the microelectronic circuit element through the patterned etch-stop layer and through the wafer.

4. The method of claim 2, further including an additional step, after the step of patterning, of

forming an electrical connection to the wafer through the patterned etch-stop layer.

5. The method of claim 1, wherein the etchable layer is silicon, the etch-stop layer is silicon dioxide, and the wafer is single-crystal silicon.

6. The method of claim 1, wherein the second substrate contains a second microelectronic circuit element.

7. The method of claim 6, wherein the step of attaching includes the step of

making an electrical contact from the microelectronic circuit element on the wafer of the first substrate to the second microelectronic circuit element on the second substrate.

8. The method of claim 1, wherein the step of attaching includes the steps of

placing a layer of epoxy between the second substrate and the wafer portion of the first substrate, and

degassing and curing the epoxy.

9. The method of claim 1, further including an additional step, after the step of attaching and before the step of etching, of

fixing the second substrate to an etching support that is resistant to attack by an etchant.

10. The method of claim 1, wherein the step of etching includes the step of

contacting the etchable layer to a liquid etchant that attacks the etchable layer rapidly and the etch-stop layer slowly.

11. A method of fabricating a microelectronic device, comprising the steps of:

furnishing a first substrate having an etchable layer, an etch-stop layer overlying the etchable layer, and a wafer overlying the etch-stop layer;

forming a microelectronic circuit element in the exposed side of the wafer of the first substrate opposite the side overlying the etch-stop layer;

attaching the wafer of the first substrate to a second substrate, the second substrate having a second microelectronic circuit element therein;

making an electrical contact from the microelectronic circuit element in the wafer of the first substrate to the second microelectronic circuit element on the second substrate; and

etching away the etchable layer of the first substrate down to the etch-stop layer; and

forming an electrical connection to the microelectronic circuit element in the wafer of the first substrate through the etch-stop layer.

12. The method of claim 11, wherein the etchable layer is silicon, the etch-stop layer is silicon dioxide, and the wafer is single-crystal silicon.

13. A method of fabricating a microelectronic device, comprising the steps of:

furnishing a first substrate having a silicon etchable layer, a silicon dioxide etch-stop layer overlying the silicon layer, and a single-crystal silicon wafer overlying the etch-stop layer, the wafer having a front surface not contacting the silicon dioxide layer;

forming a microelectronic circuit element in the front surface of the single-crystal silicon wafer;

attaching the front surface of the single-crystal silicon wafer to a first side of a second substrate; and

etching away the silicon etchable layer down to the silicon dioxide etch-stop layer using an etchant that attacks the silicon layer but not the silicon dioxide layer.

14. The method of claim 13, further including an additional-step, after the step of etching, of

patterning the etch-stop layer.

15. The method of claim 14, further including an additional step, after the step of patterning, of

forming an electrical connection to the microelectronic circuit element through the patterned etch-stop layer and through the wafer.

16. The method of claim 14, further including an additional step, after the step of patterning, of

forming an electrical connection to the wafer through the patterned etch-stop layer.

17. The method of claim 13, wherein the silicon etchable layer of the first substrate is about 500 micrometers in thickness, the silicon dioxide etch-stop layer of the first substrate is about 1 micrometer in thickness, and the wafer of the first substrate is from about 30 nanometers to about micrometers in thickness.

18. The method of claim 13, wherein the step of attaching includes the steps of

placing a layer of epoxy between the second substrate and the front surface of the single-crystal silicon wafer, and

degassing and curing the epoxy.