Pipelined video encoder architecture

  • US 5,592,399 A
  • Filed: 05/26/1993
  • Issued: 01/07/1997
  • Est. Priority Date: 05/26/1993
  • Status: Expired due to Term
First Claim
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1. A video accelerator for a video processing system, wherein the video accelerator is adapted to perform hardwired decode functions to decode encoded video signals to accelerate video decode processing of the video processing system, comprising:

  • a run-length decoder, a dequantizer coupled to the run-length decoder, and an inverse transformer coupled to the dequantizer, wherein the video accelerator comprises a pipelined architecture such that;

    the run-length decoder transforms a first set of signals into run-length decoded signals;

    the dequantizer transforms a second set of signals into dequantized signals simultaneously with the transformation of the first set of signals by the run-length decoder;

    the inverse transformer transforms a third set of signals into inverse transformed signals simultaneously with the transformation of the first set of signals by the run-length decoder and the transformation of the second set of signals by the dequantizer;

    the run-length decoder transmits the run-length decoded signals directly to the dequantizer for dequantizing; and

    the dequantizer transmits the dequantized signals directly to the inverse transformer for inverse transforming.

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