Multiple operations employing divided arithmetic logic unit and multiple flags register
First Claim
1. A data processing apparatus comprising:
- an options register storing an indication of a number of sections selected from a plurality of possible number of sections;
an arithmetic logic unit connected to said options register having a first N-bit data input for a first N-bit digital input and a second N-bit data input for a second N-bit digital input, said arithmetic logic unit being divisible into said plurality of possible number of sections and divided into a plurality of sections equal in number to said indication of said number of sections stored in said options register, each section generating at a corresponding output a digital resultant signal representing a combination of respective subsets of said first and second multibit digital inputs of said inputs, and said arithmetic logic unit including a status detector generating a plurality of single bit status signals equal in number to said indication of said number of sections stored in said options register, each single bit status signal indicative of said digital resultant signal of a corresponding section of said arithmetic logic unit; and
a multiple flags register connected to said options register and said status detector having a number of bit storage locations greater than a greatest possible number of sections of said arithmetic logic unit, said multiple flags register connected to said status detector of said arithmetic logic unit for storing in predetermined locations within said multiple flags register said plurality of single bit status signals equal in number to said indication of said number of sections stored in said options register.
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Abstract
A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a combination of respective subsets of first and second multibit digital inputs. The arithmetic logic unit includes a status detector generating a single bit status signal indicative of said digital resultant signal of a corresponding section of the arithmetic logic unit. These single bit status signals are stored in predetermined locations within a multiple flags register. An options register stores an indication of the number of sections selected from a plurality of possible number of sections into which the arithmetic logic unit is divided. The arithmetic logic unit is further connected to the multiple flags register so that each section selects for output either corresponding bits of the first multibit digital input or the second multibit digital input dependent upon the digital state of a corresponding single status bit in the multiple flags register. This technique permits a variety of functions such as add with saturation, maximum, pixel transparency and color expansion.
180 Citations
39 Claims
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1. A data processing apparatus comprising:
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an options register storing an indication of a number of sections selected from a plurality of possible number of sections; an arithmetic logic unit connected to said options register having a first N-bit data input for a first N-bit digital input and a second N-bit data input for a second N-bit digital input, said arithmetic logic unit being divisible into said plurality of possible number of sections and divided into a plurality of sections equal in number to said indication of said number of sections stored in said options register, each section generating at a corresponding output a digital resultant signal representing a combination of respective subsets of said first and second multibit digital inputs of said inputs, and said arithmetic logic unit including a status detector generating a plurality of single bit status signals equal in number to said indication of said number of sections stored in said options register, each single bit status signal indicative of said digital resultant signal of a corresponding section of said arithmetic logic unit; and a multiple flags register connected to said options register and said status detector having a number of bit storage locations greater than a greatest possible number of sections of said arithmetic logic unit, said multiple flags register connected to said status detector of said arithmetic logic unit for storing in predetermined locations within said multiple flags register said plurality of single bit status signals equal in number to said indication of said number of sections stored in said options register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A data processing apparatus comprising:
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an options register storing an indication of a number of sections selected from a plurality of possible number of sections; a multiple flags register connected to said options register, said multiple flags register having a number of bit storage locations greater than a greatest. possible number of sections of said indication of said number of sections stored in said options register, for storing in predetermined locations a plurality of single status bits equal in number to said number of indications of said options register; and an arithmetic logic unit connected to said options register and said multiple flags register having a first N-bit data input for a first N-bit digital input and a second N-bit data input for a second N-bit digital input, said arithmetic logic unit being divisible into said plurality of possible number of sections and divided into a plurality of sections equal in number to said indication of said number of sections stored in said options register, each section generating at a corresponding output a digital resultant signal equal to either corresponding bits of said first multibit digital input or corresponding bits of said second multibit digital input dependent upon the digital state of a corresponding one of said plurality of single status bits in said multiple flags register equal in number to said indication of said number of sections stored in said options register. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. The method of addition with saturation comprising the steps of:
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storing an indication of a number of sections selected from a plurality of possible number of sections; dividing an arithmetic logic unit into a plurality of sections equal in number to said stored indication of said selected number of sections, each section forming a digital resultant signal for respective subsets of a first multibit digital input and a second multibit digital input; employing said divided arithmetic logic unit to form a sum for respective subsets of a first multibit digital input and a second multibit digital input; generating a plurality of single bit status signal equal in number to said stored indication of said selected number of sections, each indicative of whether a corresponding one of said plurality of sums generates a carry out; storing said plurality of single bit status signals corresponding to each of said plurality of sums in a register having a number of bit storage locations greater than a greatest possible number of sections of said stored indication; and employing said divided arithmetic logic unit to select for each section either said corresponding sum if said stored single bit status signals equal in number to said stored indication of said selected number of sections indicates said corresponding sum failed to generate a carry out or a corresponding saturated value if said stored single bit status signals equal in number to said stored indication of said selected number of sections indicates said corresponding sum generated a carry out. - View Dependent Claims (34)
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35. The method of determining a maximum value comprising the steps of:
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storing an indication of a number of sections selected from a plurality of possible number of sections; dividing an arithmetic logic unit into a plurality of sections equal in number to said stored indication equal in number to said stored indication of said selected number of sections, each section forming a digital resultant signal for respective subsets of a first multibit digital input and a second multibit digital input; employing said divided arithmetic logic unit to form a difference for respective subsets of a first multibit digital input and a second multibit digital input; generating a plurality of single bit status signal equal in number to said stored indication of said selected number of sections, each indicative of whether a corresponding one of said plurality of differences generates a borrow out; storing said plurality of single bit status signals corresponding to each of said plurality of differences in a register having a number of bit storage locations greater than a greatest possible number of sections of said stored indication; and employing said divided arithmetic logic unit to select for each section either said respective bits of said second multibit digital input if said stored single bit status signals equal in number to said stored indication of said selected number of sections indicates said corresponding difference failed to generate a borrow out or said respective bits of said second multibit digital input if said stored single bit status signals equal in number to said stored indication of said selected number of sections indicates said corresponding difference generated a borrow out.
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36. The method of pixel transparency comprising the steps of:
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storing an indication of a number of sections selected from a plurality of possible number of sections; dividing an arithmetic logic unit into a plurality of sections equal in number to said stored indication of said selected number of sections, each section forming a digital resultant signal for respective subsets of a first multibit digital input and a second multibit digital input; employing said divided arithmetic logic unit to compare for respective subsets of a first multibit digital input representing source pixel color codes and a second multibit digital input in which each section is a transparent color code; generating a plurality of single bit status signal equal in number to said stored indication of said selected number of sections, each indicative of whether a corresponding one of said corresponding source pixel color code equals said transparent color code; storing said plurality of single bit status signals corresponding to each of said plurality of comparisons in a register having a number of bit storage locations greater than a greatest possible number of sections of said stored indication; and employing said divided arithmetic logic unit to select for each section either said respective bits of said source pixel color code if said stored single bit status signals equal in number to said stored indication of said selected number of sections indicates said corresponding comparison failed to generate an equal signal or said respective bits of a destination pixel color code if said stored single bit status signals equal in number to said stored indication of said selected number of sections indicates said corresponding comparison generated an equal signal.
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37. A method for guided copying comprising the steps of:
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storing an indication of a number of sections selected from a plurality of possible number of sections; loading a multiple flags register with a plurality of single status bits equal in number to said stored indication of said selected number of sections, said multiple flags register having a number of bit storage locations greater than a greatest possible number of sections of said stored indication; dividing an arithmetic logic unit into a plurality of sections equal in number to said stored indication of said selected number of sections, each section forming a digital resultant signal for respective subsets of a first multibit digital input and a second multibit digital input; and employing said divided arithmetic logic unit to generate at a corresponding output a digital resultant signal equal to either corresponding bits of said first multibit digital input or corresponding bits of said second multibit digital input dependent upon the digital state of a corresponding one of said plurality of single status bits in said multiple flags register equal in number to said stored indication of said selected number of sections. - View Dependent Claims (38, 39)
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Specification