Low voltage SOI (Silicon On Insulator) logic circuit

• US 5,594,371 A
• Filed: 06/27/1995
• Issued: 01/14/1997
• Est. Priority Date: 06/28/1994
• Status: Expired due to Term

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone Corporation
• Inventors: Douseki, Takakuni
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/495,785
• Time in Patent Office: 567 Days
• Field of Search: 326/122, 326/119, 326/83
• US Class Current: 326/119
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A SOI (Silicon On Insulator) logic circuit including serially connected power switching SOI MOSFETs (44, 45) and a logic circuit (43) constituted by SOI MOSFETs. The bodies of the MOSFETs of the logic circuit are made floating state, thereby implementing low threshold voltage MOSFETs. The bodies of the power switching MOSFETs are biased to power supply potentials, thereby implementing high threshold MOSFETs. The low threshold voltage MOSFETs enable the logic circuit to operate at a high speed in an active mode, and the high threshold voltage power switching MOSFETs can reduce the power dissipation in a sleep mode.

Claims

1. A low voltage SOI (Silicon On Insulator) logic circuit comprising:

a first power supply line;

a second power supply line;

a first SOI FET (Field Effect Transistor) whose source and body are connected to said first power supply line;

a second SOI FET whose source and body are connected to said second power supply line; and

a logic circuit connected between a drain of said first SOI FET and a drain of said second SOI FET;

wherein said logic circuit is constituted by a plurality of SOI FETs whose bodies are made floating state, and a connection between said first power supply line ahd said logic circuit and a connection between said second power supply line and said logic circuit are switched by a signal supplied to a gate of said first SOI FET and a gate of said second SOI FET.

2. The low voltage SOI logic circuit as claimed in claim 1, wherein a carrier concentration in said bodies of said SOI FETs constituting said logic circuit is adjusted such that said bodies of said SOI FETs constituting said logic circuit are made fully depleted, and a carrier concentration in said bodies of said first SOI FET and said second SOI FET is adjusted such that said bodies of said first SOI FET and said second SOI FET are partially depleted.

3. The low voltage SOI logic circuit as claimed in claim 1, wherein a carrier concentration in said bodies of said SOI FETs constituting said logic circuit is adjusted such that a depletion layer width W given by the following equation (A) is equal to or greater than depth of said bodies of said SOI FETs constituting said logic circuit, and a carrier concentration in said bodies of said first SOI FET and said second SOI FET are adjusted such that said depletion layer width W given by the following equation (A) is less than depth of said bodies of said first SOI FET and said second SOI FET:

space="preserve" listing-type="equation">W={2.di-elect cons..sub.si ·

2φ

.sub.f /(q·

N.sub.body)}.sup.1/2 (A)

where

.di-elect cons._si is the dielectric constant of silicon,

φ

_f is the Fermi potential of silicon,

q is the charge of the electron, and

N_body is the carrier concentration in the body.

4. The low voltage SOI logic circuit as claimed in claim 3, wherein said depth of said bodies of said SOI FETs constituting said logic circuit is made equal to or less than 100 nm, and said carrier concentration in said bodies of said SOI FETs constituting said logic circuit is made equal to or less than 1×

10¹⁷ cm^-3 to fully deplete said bodies, and said depth of said bodies of said first SOI FET and said second SOI FET is made equal to or less than 100 nm, and said carrier concentration in said bodies of said first SOI FET and said second SOI FET is set greater than 1×

10¹⁷ cm^-3 to partially deplete said bodies.

5. A low voltage SOI (Silicon On Insulator) logic circuit comprising:

a first power supply line;

a second power supply line;

a first SOI FET (Field Effect Transistor) whose source is connected to said first power supply line, and whose body is connected to a gate of said first SOI FET;

a second SOI FET whose source is connected to said second power supply line, and whose body is connected to a gate of said second SOI FET; and

a logic circuit connected between a drain of said first SOI FET and a drain of said second SOI FET;

wherein said logic circuit is constituted by a plurality of SOI FETs whose bodies are made floating state, and a connection between said first power supply line and said logic circuit and a connection between said second power supply line and said logic circuit are switched by a signal supplied to said gate of said first SOI FET and said gate of said second SOI FET.

6. The low voltage SOI logic circuit as claimed in claim 5, wherein a carrier concentration in said bodies of said SOI FETs constituting said logic circuit is adjusted such that said bodies of said SOI FETs constituting said logic circuit are made fully depleted, and a carrier concentration in said bodies of said first SOI FET and said second SOI FET is adjusted such that said bodies of said first SOI FET and said second SOI FET are partially depleted.

7. The low voltage SOI logic circuit as claimed in claim 5, wherein a carrier concentration in said bodies of said SOI FETs constituting said logic circuit is adjusted such that a depletion layer width W given by the following equation (A) is equal to or greater than depth of said bodies of said SOI FETs constituting said logic circuit, and a carrier concentration in said bodies of said first SOI FET and said second SOI FET are adjusted such that said depletion layer width W given by the following equation (A) is less than depth of said bodies of said first SOI FET and said second SOI FET:

space="preserve" listing-type="equation">W={2.di-elect cons..sub.si ·

2φ

.sub.f /(q·

N.sub.body)}.sup.1/2 (A)

where

.di-elect cons._si is the dielectric constant of silicon,

φ

_f is the Fermi potential of silicon,

q is the charge of the electron, and

N_body is the carrier concentration in the body.

8. The low voltage SOI logic circuit as claimed in claim 7, wherein said depth of said bodies of said SOI FETs constituting said logic circuit is made equal to or less than 100 nm, and said carrier concentration in said bodies of said SOI FETs constituting said logic circuit is made equal to or less than 1×

10¹⁷ cm^-3 to fully deplete said bodies, and said depth of said bodies of said first SOI FET and said second SOI FET is made equal to or less than 100 nm, and said carrier concentration in said bodies of said first SOI FET and said second SOI FET is set greater than 1×

10¹⁷ cm^-3 to partially deplete said bodies.

9. A low voltage SOI (Silicon On Insulator) logic circuit comprising:

a first power supply line;

a second power supply line;

a power switching SOI FET (Field Effect Transistor) whose source and body are connected to said first power supply line; and

a logic circuit connected between a drain of said power switching SOI FET and said second power supply line;

wherein said logic circuit is constituted by a plurality of SOI FETs whose bodies are made floating state, and a connection between said first power supply line and said logic circuit is switched by a signal supplied to a gate of said power switching SOI FET.

10. The low voltage SOI logic circuit as claimed in claim 9, wherein a carrier concentration in said bodies of said SOI FETs constituting said logic circuit is adjusted such that said bodies of said SOI FETs constituting said logic circuit are made fully depleted, and a carrier concentration in said body of said power switching SOI FET is adjusted such that said body of said power switching SOI FET is partially depleted.

11. The low voltage SOI logic circuit as claimed in claim 9, wherein a carrier concentration in said bodies of said SOI FETs constituting said logic circuit is adjusted such that a depletion layer width W given by the following equation (A) is equal to or greater than depth of said bodies of said SOI FETs constituting said logic circuit, and a carrier concentration in said body of said power switching SOI FET is adjusted such that said depletion layer width W given by the following equation (A) is less than depth of said body of said power switching SOI FET:

space="preserve" listing-type="equation">W={2.di-elect cons..sub.si ·

2φ

.sub.f /(q·

N.sub.body)}.sup.1/2 (A)

where

.di-elect cons._si is the dielectric constant of silicon,

φ

_f is the Fermi potential of silicon,

q is the charge of the electron, and

N_body is the carrier concentration in the body.

12. The low voltage SOI logic circuit as claimed in claim 11, wherein said depth of said bodies of said SOI FETs constituting said logic circuit is made equal to or less than 100 nm, and said carrier concentration in said bodies of said SOI FETs constituting said logic circuit is made equal to or less than 1×

10¹⁷ cm^-3 to fully deplete said bodies, and said depth of said body of said power switching SOI FET is made equal to or less than 100 nm, and said carrier concentration of said body of said power switching SOI FET is set greater than 1×

10¹⁷ cm^-3 to partially deplete said body.

13. A low voltage SOI (Silicon On Insulator) logic circuit comprising:

a first power supply line;

a second power supply line;

a power switching SOI FET (Field Effect Transistor) whose source is connected to said first power supply line, and whose body is connected to a gate of said power switching SOI FET; and

a logic circuit connected between a drain of said power switching SOI FET and said second power supply line;

wherein said logic circuit is constituted by a plurality of SOI FETs whose bodies are made floating state, and a connection between said first power supply line and said logic circuit is switched by a signal supplied to said gate of said power switching SOI FET.

14. The low voltage SOI logic circuit as claimed in claim 13, wherein a carrier concentration in said bodies of said SOI FETs constituting said logic circuit is adjusted such that said bodies of said SOI FETs constituting said logic circuit are made fully depleted, and a carrier concentration in said body of said power switching SOI FET is adjusted such that said body of said power switching SOI FET is partially depleted.

15. The low voltage SOI logic circuit as claimed in claim 13, wherein a carrier concentration in said bodies of said SOI FETs constituting said logic circuit is adjusted such that a depletion layer width W given by the following equation (A) is equal to or greater than depth of said bodies of said SOI FETs constituting said logic circuit, and a carrier concentration in said body of said power switching SOI FET is adjusted such that said depletion layer width W given by the following equation (A) is less than depth of said body of said power switching SOI FET:

space="preserve" listing-type="equation">W={2.di-elect cons..sub.si ·

2φ

.sub.f /(q·

N.sub.body)}.sup.1/2 (A)

where

.di-elect cons._si is the dielectric constant of silicon,

φ

_f is the Fermi potential of silicon,

q is the charge of the electron, and

N_body is the carrier concentration in the body.

16. The low voltage SOI logic circuit as claimed in claim 15, wherein said depth of said bodies of said SOI FETs constituting said logic circuit is made equal to or less than 100 nm, and said carrier concentration in said bodies of said SOI FETs constituting said logic circuit is made equal to or less than 1×

10¹⁷ cm^-3 to fully deplete said bodies, and said depth of said body of said power switching SOI FET is made equal to or less than 100 nm, and said carrier concentration of said body of said power switching SOI FET is set greater than 1×

10¹⁷ cm^-3 to partially deplete said body.