Input/output data port with a parallel and serial interface
First Claim
1. An I/O data port circuit electrically connecting a parallel data bus with an input serial data bus and an output serial data bus, and selectively operable in at least a linear mode and a buffered mode, comprising:
- an interface register connected in parallel to said parallel data bus, comprising at least two flip-flops;
a temporary register comprising at least two flip-flops, serially connected to at least one of a first most significant flip-flop and a first least significant flip-flop of said interface register;
an outbound register comprising at least two flip-flops, connected in parallel to said temporary register and having at least one of a second most significant flip-flop and a second least significant flip-flop, said second most significant flip-flop connected serially with said output serial data bus; and
an inbound register comprising at least two flip-flops, connected in parallel to said temporary register and having at least one of a third most significant and a third least significant flip-flop, said third least significant flip-flop connected serially with said input serial data bus.
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Abstract
The present invention disclosed an input/output data port circuit which connects a parallel data bus with an input serial data bus and an output serial data bus. The input/output data port is selectively operable in either a linear mode or a buffered mode. The input/output port is comprised of an interface register that is connected to a parallel data bus, a serial input bus and a serial output bus; a temporary register that is serially connected to the interface register, an outbound register that is connected in parallel to the temporary register and serially connected to a serial bus; and an inbound register that is connected in parallel to the temporary register and serially connected to a serial, bus.
154 Citations
19 Claims
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1. An I/O data port circuit electrically connecting a parallel data bus with an input serial data bus and an output serial data bus, and selectively operable in at least a linear mode and a buffered mode, comprising:
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an interface register connected in parallel to said parallel data bus, comprising at least two flip-flops; a temporary register comprising at least two flip-flops, serially connected to at least one of a first most significant flip-flop and a first least significant flip-flop of said interface register; an outbound register comprising at least two flip-flops, connected in parallel to said temporary register and having at least one of a second most significant flip-flop and a second least significant flip-flop, said second most significant flip-flop connected serially with said output serial data bus; and an inbound register comprising at least two flip-flops, connected in parallel to said temporary register and having at least one of a third most significant and a third least significant flip-flop, said third least significant flip-flop connected serially with said input serial data bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A data input/output port capable of converting parallel data to serial data and serial data to parallel data, comprising:
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a first circuit portion capable of receiving a first data in serial form from a first serial bus and placing said first data on a parallel bus, said first circuit portion simultaneously capable of retrieving a second data from said parallel bus and transmitting said second data on a second serial bus, said first and second data propagating through a first same part of said first circuit portion; a second circuit portion electrically connected to said first circuit portion, said first and second circuit portions combined being capable of receiving a third data from a third serial bus, buffering said third data, and placing said third data on said parallel bus, and being capable of simultaneously receiving a fourth data from said parallel bus, buffering said fourth data, and transmitting said fourth data on a fourth data bus, said third and fourth data propagating through at least a second same part of said second circuit portion. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method for transferring a first data from a parallel bus to a first serial bus, while simultaneously transferring a second data from a second serial bus to said parallel bus such that said first data and said second data both propagate through the same circuitry, comprising the steps of:
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a) latching said first data from said parallel bus to an interface register; b) latching said second data from an inbound register to a master portion of a temporary register; c) circularly shifting said first data from said interface register to a slave portion of said temporary register; d) shifting said second data from said second serial bus to said inbound register; e) latching said first data from said slave portion of said temporary register to an outbound register; f) circularly shifting said second data from said master portion of said temporary register to said interface register; g) latching said second data from said interface register to said parallel bus; and h) shifting said first data from said outbound register to said first serial bus.
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Specification