Pipeland address memories, and systems and methods using the same
DCFirst Claim
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1. A pipelined address memory system comprising:
- a plurality of memory units, each including an array of memory cells and circuitry for accessing selected ones of said cells in said array;
a precharge bus for carrying precharge control signals;
an active bus for carrying active cycle control signals;
circuitry coupled to said precharge bus for generating said precharge control signals;
circuitry coupled to said active bus for generating said active cycle control signals;
circuitry for selectively coupling said memory units to said precharge bus for precharge; and
circuitry for selectively coupling said memory units to said active bus for active operation.
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Abstract
A dynamic random access memory device 200 includes circuitry 202 for generating a plurality of internal row address strobes. A plurality of memory banks 201 are included, each having an array 203 of dynamic random access cells and associated dynamic control circuitry. A first one of the memory banks 201 enters precharge in response to a precharged cycle of a first one of the internal row address strobes. Simultaneously, a second one of the banks 201 enters an active cycle in response to an active cycle of a second one of the internal address strobes.
37 Citations
21 Claims
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1. A pipelined address memory system comprising:
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a plurality of memory units, each including an array of memory cells and circuitry for accessing selected ones of said cells in said array; a precharge bus for carrying precharge control signals; an active bus for carrying active cycle control signals; circuitry coupled to said precharge bus for generating said precharge control signals; circuitry coupled to said active bus for generating said active cycle control signals; circuitry for selectively coupling said memory units to said precharge bus for precharge; and circuitry for selectively coupling said memory units to said active bus for active operation. - View Dependent Claims (2, 3, 4, 5)
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6. A method of operating a pipelined memory system, the pipelined memory system including a plurality of memory units, each memory unit including an array of memory cells and circuitry for accessing locations in the array, a precharge bus for carrying precharge control signals generated by associated precharge control circuitry and an active bus, for carrying active cycle control signals generated by active cycle control circuitry, the method comprising the steps of:
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coupling a first selected one of the memory units to the active bus; performing an access to a selected location in the array of the first memory unit under the control of the active cycle control signals on the active bus; coupling a second selected one of the memory units to the precharge bus; and substantially simultaneously with said step of performing an access, performing a precharge of the second memory unit under the control of the precharge control signals on the precharge bus. - View Dependent Claims (7, 8, 9, 10)
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11. A pipelined address memory system comprising:
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a plurality of independent memory units each including an array of dynamic random access memory cells, dynamic control circuitry, and an address register; a precharge bus; an active cycle bus; active clock circuitry for generating clocks for memory unit active cycle operations; precharge clock circuitry for generating clocks for memory unit precharge operations; bus control circuitry for selectively coupling a first selected one of said memory units with said active clock circuitry via said active bus during active cycle operation of said first memory unit and a second selected one of said memory units to said precharge clock circuitry for simultaneous precharge operation of said second memory unit; and an address bus for providing addresses to said address registers of said memory units for use during subsequent memory accesses during active cycle operation. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification