Pipeland address memories, and systems and methods using the same

  • US 5,598,374 A
  • Filed: 07/14/1995
  • Issued: 01/28/1997
  • Est. Priority Date: 07/14/1995
  • Status: Expired due to Term
First Claim
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1. A pipelined address memory system comprising:

  • a plurality of memory units, each including an array of memory cells and circuitry for accessing selected ones of said cells in said array;

    a precharge bus for carrying precharge control signals;

    an active bus for carrying active cycle control signals;

    circuitry coupled to said precharge bus for generating said precharge control signals;

    circuitry coupled to said active bus for generating said active cycle control signals;

    circuitry for selectively coupling said memory units to said precharge bus for precharge; and

    circuitry for selectively coupling said memory units to said active bus for active operation.

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