MPEG video decompression processor

• US 5,598,483 A
• Filed: 10/24/1994
• Issued: 01/28/1997
• Est. Priority Date: 04/13/1993
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: C-Cube Corporation (Broadcom, Inc.)
• Inventors: Purcell, Stephen C., Galbi, David E., Liao, Frank H., Tse, Yvonne C.
• Primary Examiner(s): Couso, Jose L.
• Application Number:
  US08/297,722
• Time in Patent Office: 827 Days
• Field of Search: 382/232, 382/236, 382/238, 382/239, 348/403, 348/407, 348/413
• US Class Current: 382/232
• CPC Class Codes: H03M 7/425 for the decoding process only
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/124 Quantisation
• CPC Class Codes: H04N 19/126 Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/433 characterised by techniques for memory access
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence

Abstract

A method and a structure are provided to decode intra-frame and interframe coded compressed video data. In one embodiment of the present invention, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure in accordance with the present invention communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor in the decompression structure of the present invention provides overall control to the decoder, IDCT and motion compensation coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the decoder, the IDCT and the motion compensation coprocessors.

Claims

1. An apparatus for decompressing coded compressed video signal, said apparatus being coupled to a memory, said apparatus comprising:

a bus, coupled to said memory, said bus providing read and write accesses to said memory;

a first-in-first-out (FIFO) buffer for receiving from said memory via said bus compressed video signals, said compressed video signals encoded by variable-length codes;

a decoding circuit, coupled to said FIFO buffer, for decoding the variable-length codes of said coded compressed video signals received from said FIFO buffer;

an inverse discrete cosine transform (IDCT) circuit, receiving said decoded video signals, for performing an inverse discrete cosine transform on said decoded video signals, and for providing said transformed video signals on said bus;

a motion compensation circuit, coupled to receive said transformed video signals from said bus and coupled to receive over said bus reference frames from said memory, said motion compensation circuit reconstructing video signals using said reference frames to further decode said transformed video signals, and storing said reconstructed video signals in said memory via said bus; and

a memory controller, coupled to said memory, said FIFO, said IDCT circuit, and said motion compensation circuit, for controlling memory access over said bus by said FIFO, said IDCT circuit, and said motion compensation circuit, in accordance with a predetermined priority scheme.

2. An apparatus as in claim 1, further comprising a processor for controlling said decoding circuit, said inverse discrete cosine transform circuit and said motion compensation circuit, said processor accessing over said bus instructions stored in said memory.

3. An apparatus as in claim 2, wherein said processor controls said decoding circuit, said inverse cosine transform circuit, and said motion compensation circuit by accessing, over said bus, control and data registers of said decoding circuit, said inverse cosine transform circuit, and said motion compensation circuit.

4. An apparatus as in claim 1, wherein a portion of said bus comprises a host bus for communication with a host computer.