Solid state image sensor transferring charges with high efficiency and decreased power consumption, and method of driving the same

• US 5,600,127 A
• Filed: 07/31/1995
• Issued: 02/04/1997
• Est. Priority Date: 02/23/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kimata, Masafumi
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US08/508,430
• Time in Patent Office: 554 Days
• Field of Search: 250/208.1, 348/303, 348/304, 348/308, 348/283, 257/231, 257/232, 377/34, 377/44, 377/115-117
• US Class Current: 250/208.1
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/709 Circuitry for control of the power supply
• CPC Class Codes: H04N 25/713 Transfer or readout registers; Split readout registers or multiple readout registers
• CPC Class Codes: H04N 25/73 using interline transfer [IT]

Abstract

A solid state image sensor of charge sweep architecture comprises photodetectors in two-dimension, vertical charge transfer elements and a horizontal charge transfer element. A driver circuit for the vertical charge transfer elements mounted in the solid state image sensor comprises a circuit for setting initial states of shift registers and a circulation loop line connecting an output of the shift register at the last stage to an input of the shift register at a first stage. Thus, a lower consumption power and high efficiency charge transfer are provided in the solid state image sensor.

Claims

1. A solid state image sensor comprising:

a photodetector array wherein photodetectors are arranged in two-dimension vertically and horizontally;

vertical charge transfer elements each connected to a line of photodetectors aligned vertically in said photodetector array;

a pixel line selection circuit which selects a horizontal line or a group of horizontal lines of photodetectors among said photodetectors in a horizontal blanking period and transfers signal charges stored in the photodetectors in the selected line or lines to the vertical charge transfer elements;

a driver means for supplying signals to said vertical charge transfer elements for driving the signal charges in said vertical charge transfer elements; and

a horizontal charge transfer element connected to said vertical charge transfer elements, the horizontal charge transfer element transferring signal charges transferred from said vertical charge transfer elements to the external in a next horizontal period subsequent to the horizontal blanking period;

wherein said driver means comprises shift registers of a plurality of stages each corresponding to a horizontal line of said photodetector array; and

each stage of said shift registers comprises;

transfer gates operated by clock signals and inverters connected to the transfer gates;

connection lines connecting an output of the shift register in a stage to an input of the shift register in a next stage; and

a circulation loop line connecting an output of the shift registers of the last stage in said shift registers to an input of the shift register of a first stage in said shift registers.

2. The solid state image sensor according to claim 1, wherein each of the shift registers of said driver circuit comprises a circuit for setting initial states of the shift registers in each stage.

3. The solid state image sensor according to claim 2, wherein each of the shift registers comprises:

a first transfer gate driven by a first clock signal;

a first inverter connected to the first transfer gate;

a second transfer gate connected to the first inverter and driven by a second clock signal; and

a second inverter connected to the second transfer gate; and

said circuit for setting initial states of the shift registers comprises a transistor for each shift register, a terminal of the transistor being connected to the first transfer gate and to the first inverter of the shift register, the other terminal thereof being connected to a voltage in correspondence to the initial state to be set, a gate terminal of the transistor being connected to a control signal for conduction between the two terminals.

4. The solid state image sensor according to claim 3, wherein said circuits for setting initial states for the shift registers sets one of H level voltage and L level voltage for the terminal connected to the first inverter of at least two continuous stages among the stages of the shift registers and sets the other of H level and L level voltages for the terminal for shift registers of the other stages.

5. The solid state image sensor according to claim 1, further comprising a switch means for inputting a pattern for setting the initial states of the shift registers from an external circuit, the switch means being connected between said circulation loop line and the input of the first stage of the shift register.

6. The solid state image sensor according to claim 5, wherein said switch means comprises:

a first MOS transistor connected between the input of the first stage of the shift register and the external circuit; and

a second MOS transistor connected between the circulation loop line and the input of the first state of the shift register for controlling a pattern input from the external circuit.

7. The solid state image sensor according to claim 6, wherein said external circuit comprises a storage device for storing the pattern.

8. The solid state image sensor according to claim 1, further comprising:

inverters or buffers connected to outputs of the shift registers, the inverters or buffers having a driving ability larger than the first and second inverters provided in the shift registers, said inverters or buffers providing signals to said vertical charge transfer elements for transferring signal charge along the vertical charge transfer elements.

9. The solid state image sensor according to claim 1, further comprising:

other transfer gates connected to outputs of the shift registers, the other transfer gates providing signals to said vertical charge transfer elements for transferring signal charge along the vertical charge transfer elements.

10. The solid state image sensor according to claim 1, wherein a driving ability of an inverter arranged in the shift register of the last stage connected to an input of the shift register of the first stage by said circulation loop line is larger than a counterpart inverter arranged in the last stage in each of the shift registers of the other stages.

11. The solid state image sensor according to claim 1, wherein the shift register in the last stage comprises a buffer connected after an inverter arranged in the last stage in the shift register, the buffer having a driving ability larger than the inverter arranged in the last stage in the shift register.

12. The solid state image sensor according to claim 3, further comprising:

third transfer gates connected to outputs of the shift registers, the third transfer gates providing signals to said vertical charge transfer elements for transferring signal charge along the vertical charge transfer elements.

13. The solid state image sensor according to claim 5, further comprising:

transfer gates connected to outputs of the shift registers, the transfer gates providing signals to said vertical charge transfer elements for transferring signal charge along the vertical charge transfer elements.

14. A solid state image sensor comprising;

a photodetector array wherein photodetectors are arranged in two-dimension vertically and horizontally;

vertical charge transfer elements each connected to a line of photodetectors aligned vertically in said photodetectors array;

a pixel line selection circuit which selects a horizontal line or a group of horizontal lines of photodetectors among said photodetectors in a horizontal blanking period and transfers signal charges stored in the photodetectors in the selected line or lines to the vertical charge transfer elements;

a driver means for supplying signals to said vertical charge transfer elements for driving the signal charges in said vertical charge transfer elements; and

a horizontal charge transfer element connected to said vertical charge transfer elements, the horizontal charge transfer element transferring signal charges transferred from said vertical charge transfer elements to the external in a next horizontal period subsequent to the horizontal blanking period;

wherein said driver means comprises shift registers of a plurality of stages each corresponding to a horizontal line of said photodetector array; and

each stage of said shift registers comprises;

transfer gate operated by clock signal and inverters connected to the transfer gates; and

a means for generating clock signals for driving said vertical charge transfer elements, the clock signals being of a circulating clock pattern and of a number necessary to read signal charges stored in two-dimension in a horizontal period, the number being at least twice a number of the photodetectors arranged vertically.

15. The solid state image sensor according to claim 14, wherein said means for generating clock signals comprises a storage device and shift registers driven according to a driving pattern stored in the storage device.

16. The solid state image sensor according to claim 14, wherein a number of the shift register being a number necessary to read a scan line of signal charges stored in two-dimension in a horizontal period, the number being at least twice a number of the photodetectors arranged vertically.

17. A method for driving a solid state image sensor comprising:

a photodetector array wherein photodetectors are arranged in two-dimension vertically and horizontally;

vertical charge transfer elements each connected to a line of photodetectors aligned vertically in said photodetector array;

a pixel line selection circuit which selects a horizontal line or a group of horizontal lines of photodetectors among said photodetectors in a horizontal blanking period and transfers signal charges stored in the photodetectors in the selected line or lines to the vertical charge transfer elements;

a driver means for supplying signals to said vertical charge transfer elements for driving the signal charges in said vertical charge transfer elements; and

a horizontal charge transfer element connected to said vertical charge transfer elements, the horizontal charge transfer element transferring signal charges transferred from said vertical charge transfer elements to the external in a next horizontal period subsequent to the horizontal blanking period;

wherein said driver means comprises shift registers of a plurality of stages each corresponding to a horizontal line of said photodetector array; and

each stage of said shift registers comprises;

transfer gates operated by clock signals and inverters connected to the transfer gates;

connection lines connecting an output of the shift register in a next stage; and

a circulation loop line connecting an output of the shift registers of the last stage in said shift registers to an input of the shift register of a first stage in said shift registers;

the method comprises;

a first step of resetting an input stage of the shift registers of each stage in the vertical charges transfer elements by external clocks at predetermined electrical potentials;

a second step of providing outputs of the shift registers to the vertical charge transfer elements for transfer signal charge along the vertical charge transfer elements; and

a third step of inputting the output of the shift register of a stage to an input of the shift register at a next stage and inputting the output of the shift register of the last stage to an input of the shift register at the first stage;

wherein the second and third steps are iterated.

18. The method according to claim 17, wherein said first step is performed in a time when an electric power is turned on, in a vertical blanking period, or in a horizontal blanking period.

19. The method according to claim 17, wherein the electrical potential reset in the shift registers of at least two successive stages is different from that reset in the other stages.

20. The method according to claim 17, wherein in the second step, one of the outputs of the inverters of the shift registers of each stage is input to the gate of the vertical charge transfer element, and the transfer gate is turned off when said pixel line selection circuit is operated.