Power management system for components used in battery powered applications

• US 5,603,036 A
• Filed: 02/19/1993
• Issued: 02/11/1997
• Est. Priority Date: 02/19/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven E., Garner, Richard, Kendall, Terry L., Kynett, Virgil N.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/019,617
• Time in Patent Office: 1,453 Days
• Field of Search: 395/750, 395/575, 395/550, 395/182.21, 395/182.22, 365/227, 364/707
• US Class Current: 713/322
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A control circuit for a computer component circuit which includes oscillator apparatus for providing square wave pulses at a prescribed frequency, gating apparatus for providing the square wave pulses at an output terminal for use as a clock for the component circuit, timing apparatus for sensing a period during which the component circuit has not performed an operation, and apparatus for disabling the gating apparatus for providing the square wave pulses at an output terminal.

Claims

1. A control circuit for a computer component circuit, the control circuit comprising:

a microprocessor;

a series of gates controlled by the microprocessor;

an oscillator for providing square wave pulses at a prescribed frequency;

a clock signal generation circuit coupled to the oscillator and the gates for generating clock pulses from the square wave pulses for use by the computer component circuit;

a first process run by the microprocessor to control the gates to disable the oscillator and the clock signal generation circuit at the completion of any operation by the component circuit such that the clock pulses are disabled before the square wave pulses are disabled; and

a second process run by the microprocessor to control the gates to enable the oscillator and the clock signal generation circuit in response to any command to the component circuit from a host computer.

2. A control circuit as claimed in claim 1, wherein the second process controls the gates to enable the oscillator and the clock signal generation circuit such that clock pulses are not enabled until the square wave pulses have established a full wave pattern at the prescribed frequency.

3. A computer subsystem joined to a computer system having a central processing unit and a bus, the subsystem comprising:

a microprocessor for managing the subsystem;

an oscillator for generating a repeating pattern of signals;

a clock generator for providing clock signals from the repeating pattern of signals; and

a series of gates for controlling the transfer of signals from and to the oscillator to selectively disable the oscillator and the clock generator from generating the clock signals and the repeating pattern of signals in response to commands from the microprocessor such that the clock signals are disabled before the repeating pattern of signals is disabled.

4. A computer subsystem as claimed in claim 3, wherein the gates also selectively enable the oscillator and the clock generator in response to any command from the computer system, wherein the computer subsystem further comprises:

a first plurality of flip-flop circuits for providing a first set of control signals for controlling the transfer of signals from and to the oscillator by the gates; and

a second plurality of flip-flop circuits for providing a second set of control signals for controlling the transfer of signals from and to the oscillator by the gates.

5. A computer subsystem as claimed in claim 4, wherein the microprocessor provides a delay such that the clock signals are not enabled until the repeating pattern of signals has established a full wave pattern.

6. A computer system, comprising:

a central processing unit;

a main memory;

a bus for transferring signals within the computer system; and

a subsystem joined to the bus, the subsystem comprising

a control circuit that includes

a microprocessor for managing the subsystem,

an oscillator for generating a repeating pattern of signals,

a clock generator for providing clock signals from the repeating pattern of signals, and

a series of gates for controlling the transfer of signals from and to the oscillator to selectively disable the oscillator and the clock generator from generating the clock signals and the repeating pattern of signals in response to the completion of any operation by the subsystem.

7. A computer system as claimed in claim 6, wherein the gates also selectively enable the oscillator and the clock generator to generate the clock signals and the repeating pattern of signals in response to any command from the central processing unit, wherein the control circuit further comprises:

circuitry for providing a first set of control signals for controlling the transfer of signals from and to the oscillator by the series of gates, and

circuitry for providing a second set of control signals for controlling the transfer of signals from and to the oscillator by the series of gates.

8. A computer system as claimed in claim 7, wherein the microprocessor provides a delay such that the clock signals are not enabled until the repeating patter of signals has established a full wave pattern.

9. A computer system as claimed in claim 6, wherein the gates selectively disable the oscillator and the clock generator such that the clock signals are disabled before the repeating pattern of signals is disabled.

10. A method for controlling the use of power in a computer subsystem including a microprocessor for managing the subsystem, an oscillator for generating a repeating pattern of signals, and a clock generator for providing clock signals from the repeating pattern of signals, comprising the steps of:

selectively disabling the generation of the clock signals and the repeating pattern of signals in response to commands from the microprocessor after the termination of any operation by a host computer which utilizes the computer subsystem such that the clock signals are first disabled before the repeating pattern of signals is disabled, and

enabling the generation of the clock signals and the repeating pattern of signals in response to any command to the computer subsystem from a host computer system such that the clock signals are not enabled until the repeating pattern of signals has established a full wave pattern.