Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors

• US 5,613,146 A
• Filed: 06/07/1995
• Issued: 03/18/1997
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Guttag, Karl M., Balmer, Keith, Gove, Robert J., Ing-Simmons, Nicholas K.
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US08/483,658
• Time in Patent Office: 650 Days
• Field of Search: 395/800
• US Class Current: 712/20
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses

Abstract

There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and an inter-processor communication link allows the processors to communicate with each other for the purpose of establishing operational modes. A parameter memory, accessible via the crossbar switch, is used in conjunction with the communication link for control purposes. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Claims

1. A multi-processor system operating in a selected one of a plurality of modes comprising:

a plurality of processors, each processor having a data port and a separate instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;

a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors and at least one parameter memory;

a switch matrix connected to said data port and said instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said data port of each of said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, said switch matrix further connecting said instruction port of each processor to said corresponding instruction memory, said switch matrix connecting any of said plurality of processors for access to said at least one parameter memory regardless of said operational mode; and

an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode, said interprocessor communication bus transmitting a parameter read signal from any processor to any other selected processor to read data stored in said at least one parameter memory.

2. The multi-processor system claimed in claim 1, further comprising:

an external memory for storing instructions for each of said processors;

wherein each instruction memory stores only a portion of the instructions for the corresponding processor; and

wherein each processor includes;

a program counter having stored therein an address of a next instruction,

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address,

a cache logic circuit connected to said program counter for determining if the instruction corresponding to the address stored in said program counter is stored in said corresponding instruction memory,

said cache logic circuit of each processor except said predetermined first processor being disabled when said switch matrix is in said single instruction multiple data mode; and

said multi-processor system further comprising a transfer processor connected to said cache logic circuit of each of said processors, said switch matrix and said external memory, said transfer processor transferring an instruction corresponding to the address stored in said program counter of one of said processors from said external memory to said corresponding instruction memory via said switch matrix if said corresponding cache logic circuit indicates the instruction is not stored in said corresponding instruction memory.

3. A multi-processor system operating in a selected one of a plurality of modes comprising:

a plurality of processors, each processor having a data port and an instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;

a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors;

a switch matrix connected to said data port and said instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, one of said operational modes of said switch matrix being a multiple instruction multiple data mode, said switch matrix connecting processors to memory in said multiple instruction multiple data mode whereby;

each of said processors accesses instructions via said instruction port and said switch matrix from said corresponding instruction memory for supply via said switch matrix to said instruction port of said processor, and

each of said processors accesses data via said data port and said switch matrix within any of said plurality of memories except said instruction memories; and

an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode.

4. The multi-processor system claimed in claim 3, further comprising:

an external memory for storing instructions for each of said processors;

wherein each instruction memory stores only a portion of the instructions for the corresponding processor; and

wherein each processor includes;

a program counter having stored therein an address of a next instruction,

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address;

a cache logic circuit connected to said program counter for determining if the instruction corresponding to the address stored in said program counter is stored in said corresponding instruction memory; and

said multi-processor system further comprising a transfer processor connected to said cache logic circuit of each of said processors, said switch matrix and said external memory, said transfer processor transferring an instruction corresponding to the address stored in said program counter of one of said processors from said external memory to said corresponding instruction memory via said switch matrix if said corresponding cache logic circuit indicates the instruction is not stored in said corresponding instruction memory.

5. A multi-processor system operating in a selected one of a plurality of modes comprising:

a plurality of processors, each processor having a data port and a separate instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;

a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors;

a switch matrix connected to said data port and said instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, one of said operational modes of said switch matrix is a concurrent single instruction multiple data and multiple instruction multiple data mode wherein a first subset of said plurality of processors operate in said single instruction multiple data mode and a second subset of said plurality of processors operate in said multiple instruction multiple data mode, said switch matrix connecting processors to memory in said concurrent single instruction multiple data and multiple instruction multiple data mode whereby;

a predetermined one of said processors of said first subset of processors accesses instructions via said instruction port and said switch matrix from said corresponding instruction memory for supply via said switch matrix to said instruction port of each of said processors of said first subset of processors,

each of said processors of said second subset of processors accesses instructions via said instruction port and said switch matrix from said corresponding instruction memory for supply via said switch matrix to said instruction port of said processor, and

each of said processors accesses data via said data port and said switch matrix within any of said plurality of memories except said instruction memory corresponding to said predetermined one of said processors of said first subset of processors and said instruction memories corresponding to said processors of said second subset of processors; and

an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode.

6. A multi-processor system operating in a selected one of a plurality of modes comprising:

a plurality of processors, each processor having a data port and a separate instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;

a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors;

a switch matrix connected to said data port and said instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, one of said operational modes of said switch matrix is a synchronized multiple instruction multiple data mode, said switch matrix connecting processors to memory in said synchronized multiple instruction multiple data mode whereby;

each of said processors accesses instructions via said instruction port and said switch matrix from said corresponding instruction memory for supply via said switch matrix to said instruction port of said processor, each such instruction access deferred until signals on said interprocessor communication bus indicates that all processors are ready for instruction access, and

each of said processors accesses data via said data port and said switch matrix within any of said plurality of memories except said instruction memories; and

an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode.

7. A multi-processor system operating in a selected one of a plurality of modes comprising:

a plurality of processors, each processor having a first data port, a second data port and a separate instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;

a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors, said plurality of memories further including a predetermined number of data memories corresponding to each of said plurality of processors;

a switch matrix connected to said first, data port, said second data port and said separate instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, said plurality of memories consists of an instruction memory corresponding to each processor and a predetermined number of data memories corresponding to each processor, said switch matrix connecting said second data port of each processor only to said data memories corresponding to said processor; and

an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode.