Ferroelectric memory and method for controlling operation of the same
First Claim
1. A ferroelectric memory comprising a plurality of pairs of data signal lines for outputting and receiving data, a plurality of selection signal lines selected in accordance with an address signal, and a plurality of memory cells, wherein each memory cell is arranged along a corresponding pair of data signal lines of said plurality of pairs of data signal lines, wherein said memory cell is controlled by a corresponding one of said selection line signals, and wherein each said memory cells includesat least one ferroelectric capacitor having a capacitor dielectric comprising a ferroelectric material disposed between a pair of opposing electrodes, at least one switching means connected to said ferroelectric capacitor and one data signal line of said corresponding pair of data signal lines,wherein polarized conditions of said ferroelectric capacitor correspond to conditions of stored data in said ferroelectric capacitor, andwherein when a first voltage is applied between the opposing electrodes of said ferroelectric capacitor, a current flows between said ferroelectric capacitor and the corresponding data signal line, depending upon the polarized condition of said ferroelectric capacitor, and a voltage appears on the corresponding pair of data signal lines due to the current and said voltage is detected for the purpose of reading out the stored data;
- a means connected to the corresponding one pair of data signal lines for detecting a voltage difference appearing between the corresponding pair of data signal lines; and
a means connected to at least one data signal line of the corresponding pair of data signal lines for temporarily controlling a parasitic capacitance of said at least one data signal line of the corresponding pair of data signal lines to obtain an optimum capacitance value when said stored data is read out from a memory cell, and wherein said optimum value minimizes a variation of the voltage on said data signal line caused by factors other than the current flowing between said ferroelectric capacitor and said data signal line.
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Accused Products
Abstract
A ferroelectric memory includes a circuit for temporarily controlling a parasitic capacitance of a pair of data signal lines to an optimum value when data is read out from a memory cell, for the purpose of minimizing a variation of the voltage on the pair of data signal lines caused by factor other than the current caused due to the polarization of the ferroelectric capacitor. Thus, a voltage not smaller than the coercive voltage can be applied between the opposing electrodes of the ferroelectric capacitor, with the result that a sufficient read-out signal voltage can be obtained.
36 Citations
33 Claims
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1. A ferroelectric memory comprising a plurality of pairs of data signal lines for outputting and receiving data, a plurality of selection signal lines selected in accordance with an address signal, and a plurality of memory cells, wherein each memory cell is arranged along a corresponding pair of data signal lines of said plurality of pairs of data signal lines, wherein said memory cell is controlled by a corresponding one of said selection line signals, and wherein each said memory cells includes
at least one ferroelectric capacitor having a capacitor dielectric comprising a ferroelectric material disposed between a pair of opposing electrodes, at least one switching means connected to said ferroelectric capacitor and one data signal line of said corresponding pair of data signal lines, wherein polarized conditions of said ferroelectric capacitor correspond to conditions of stored data in said ferroelectric capacitor, and wherein when a first voltage is applied between the opposing electrodes of said ferroelectric capacitor, a current flows between said ferroelectric capacitor and the corresponding data signal line, depending upon the polarized condition of said ferroelectric capacitor, and a voltage appears on the corresponding pair of data signal lines due to the current and said voltage is detected for the purpose of reading out the stored data; -
a means connected to the corresponding one pair of data signal lines for detecting a voltage difference appearing between the corresponding pair of data signal lines; and a means connected to at least one data signal line of the corresponding pair of data signal lines for temporarily controlling a parasitic capacitance of said at least one data signal line of the corresponding pair of data signal lines to obtain an optimum capacitance value when said stored data is read out from a memory cell, and wherein said optimum value minimizes a variation of the voltage on said data signal line caused by factors other than the current flowing between said ferroelectric capacitor and said data signal line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for reading out data from a ferroelectric memory, wherein said memory comprises, a plurality of pairs of data signal lines for outputting and receiving data, a plurality of selection signal lines selected in accordance with an address signal, and a plurality of memory cells, wherein each memory cell is arranged along a corresponding pair of data signal lines of said plurality of pairs of data signal lines, and wherein each said memory cell includes
at least one ferroelectric capacitor having a capacitor dielectric comprising a ferroelectric material disposed between a pair of opposing electrodes, at least one switching means connected to said ferroelectric capacitor and one data signal line of said corresponding pair of data signal lines, wherein said memory cell is controlled by a corresponding one of said selection signal lines, wherein polarized conditions of said ferroelectric capacitor correspond to conditions of stored data in said ferroelectric capacitor, and wherein when a first voltage is applied between the opposing electrodes of said ferroelectric capacitor, a current flows between said ferroelectric capacitor and the corresponding data signal line, and a voltage appears on the corresponding pair of data signal lines due to the current and said voltage is detected for the purpose of reading out the stored data; -
a means connected to the corresponding one pair of data signal lines for detecting a voltage difference appearing between the corresponding pair of data signal lines; and a means connected to at least one data signal line of the corresponding pair of data signal lines for temporarily controlling a parasitic capacitance of said at least one data signal line of the corresponding pair of data signal lines to obtain an optimum capacitance value when said stored data is read out from a memory cell, said method for reading of data from said memory cell comprising the steps of; setting said optimum capacitance value to minimize a variation of the voltage on said data signal line cause by factors other than the current; setting the corresponding data signal line connected to said memory cell to be read out to a second voltage; setting a plate line connected to said memory cell to be read out to a third voltage, wherein said third voltage is different from said second voltage; setting said selection signal line connected to said memory cell to be read out to a fifth voltage for selecting said memory cell to be read out, so that a voltage difference is caused to occur between the opposing electrodes of said ferroelectric capacitor, whereby a signal corresponding to the data stored in said memory cell to be read out is outputted to the corresponding data signal line. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method for reading data from a ferroelectric memory wherein said memory comprises a plurality of pairs of data signal lines for outputting and receiving data, a plurality of selection signal lines selected in accordance with an address signal, and a plurality of memory cells, wherein each memory cell is arranged along a corresponding pair of data signal lines of said plurality of pairs of data signal lines, and wherein each said memory cell includes:
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at least one ferroelectric capacitor having a capacitor dielectric comprising a ferroelectric material disposed between a pair of opposing electrodes, at least one switching means connected to said ferroelectric capacitor and one data signal line of said corresponding pair of data signal lines, wherein said memory cell is controlled by a corresponding one of said selection signal lines, wherein polarized conditions of said ferroelectric capacitor correspond to conditions of stored data in said ferroelectric capacitor, and wherein when a first voltage is applied between the opposing electrodes of said ferroelectric capacitor, a current flows between said ferroelectric capacitor and the corresponding data signal line, and a voltage appears on the corresponding pair of data signal lines due to the current and said voltage is detected for the purpose of reading out the stored data; a means connected to the corresponding one pair of data signal lines for detecting a voltage difference appearing between the corresponding pair of data signal lines; and a means connected to at least one data signal line of the corresponding pair of data signal lines for temporarily controlling a parasitic capacitance of said at least one data signal line of the corresponding pair of data signal lines to obtain an optimum capacitance value when said stored data is read out from a memory cell, and wherein said optimum value minimizes a variation of the voltage on said data signal line caused by factors other than the current said ferroelectric capacitor, said method for reading data from said memory cell comprising the steps of setting the corresponding data signal line connected to said memory cell to be read out to a second voltage, setting a plate line connected to said memory cell to be read out to a third voltage, wherein said third voltage is a fixed voltage different from said second voltage, setting said selection signal line connected to said memory cell to be read out to a fourth voltage for selecting said memory cell to be read out, so that a voltage difference is caused to occur between the opposing electrodes of said ferroelectric capacitor, whereby a signal corresponding to the data stored in said memory cell to be read out is outputted to the corresponding data signal line. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33)
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Specification