Electrically programmable read-only memory cell
First Claim
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1. A semiconductor device including an array of electrically programmable read-only memory cells comprising:
- a semiconductor substrate having a first conductivity type;
a first well region having a second conductivity type that is opposite the first conductivity type, wherein the first well region lies within the substrate;
a second well region having the first conductivity type, wherein the second well region lies within the first well region;
a third well region having the first conductivity type, wherein the third well region lies within the first well region and is spaced apart from the second well region;
a first plurality of floating gates overlying the first well region, wherein;
the first plurality of floating gates includes a second plurality of floating gates and a third plurality of floating gates;
the second plurality of floating gates overlie the second well region; and
the third plurality of floating gates overlie the third well region;
an intergate dielectric layer lying adjacent to the first plurality of floating gates; and
a first word line and a second word line lying adjacent to the intergate dielectric layer and overlying the first well region.
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Abstract
EPROM cells include T-shaped floating gates (61, 171) and control gates that surround virtually all of the floating gates (61, 171) except for the portion of the floating gates (61, 171) that lie on a gate dielectric layer (51, 151). The EPROM cells may include customized well regions (22, 122) to allow flash erasing or individual cell erasing for electrically erasable EPROMs. Many different configurations of the memory cells are possible. The configurations of the source regions, drain regions, and well regions (22, 122) may be determined by how a user of the memory cells wants to program or erase the memory cells.
51 Citations
4 Claims
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1. A semiconductor device including an array of electrically programmable read-only memory cells comprising:
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a semiconductor substrate having a first conductivity type; a first well region having a second conductivity type that is opposite the first conductivity type, wherein the first well region lies within the substrate; a second well region having the first conductivity type, wherein the second well region lies within the first well region; a third well region having the first conductivity type, wherein the third well region lies within the first well region and is spaced apart from the second well region; a first plurality of floating gates overlying the first well region, wherein; the first plurality of floating gates includes a second plurality of floating gates and a third plurality of floating gates; the second plurality of floating gates overlie the second well region; and the third plurality of floating gates overlie the third well region; an intergate dielectric layer lying adjacent to the first plurality of floating gates; and a first word line and a second word line lying adjacent to the intergate dielectric layer and overlying the first well region. - View Dependent Claims (2, 3, 4)
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Specification