Memory system

• US 5,621,682 A
• Filed: 12/28/1994
• Issued: 04/15/1997
• Est. Priority Date: 12/28/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanzawa, Toru, Tanaka, Tomoharu
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/364,997
• Time in Patent Office: 839 Days
• Field of Search: 365/185.03, 365/185.09, 365/200, 37/40.1, 37/40.2
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

According to the present invention, a memory system comprises storing section having a plurality of memory elements each of which stores one of n-value storage states corresponding to data "0", "1", . . . , "n-1", and including a plurality of information memory elements for storing n-value information data and a plurality of check memory elements for storing check data, converting section for respectively converting the information data and the check data stored in the memory elements into binary codes having a plurality of bits each constituted by 0 or 1, the binary codes corresponding to the information data and the check data, and detecting/correcting section for detecting and correcting an error on the basis of the binary codes corresponding to the check data and the information data.

Claims

1. A memory system comprising:

storing means having a plurality of memory elements each of which stores one of n-value storage states corresponding to data "0", "1", . . . , "n-1", said storing means including a plurality of information memory elements for storing n-value information data and a plurality of check memory elements for storing check data;

converting means for respectively converting the information data and the check data stored in said plurality of memory elements into binary codes having a plurality of bits each constituted by 0 or 1, the binary codes corresponding to the information data and the check data; and

detecting/correcting means for detecting and correcting an error on the basis of said binary codes corresponding to the check data and the information data.

2. A system according to claim 1, wherein said converting means includes means for converting the information data and check data into binary codes including intermediate binary codes which are combinations of binary codes each of which data is stored in one of said plurality of memory elements.

3. A system according to claim 1, wherein said storing means stores the n-value information data by combinations of said plurality of memory elements.

4. A system according to claim 1, wherein said information memory element includes

a second converting means for causing said check memory element to generate a binary code corresponding to data to be stored in one of said plurality of memory elements, and

writing means for causing said plurality of memory elements to perform n-value storage on the basis of the binary code.

5. A system according to claim 1, wherein said converting means includes means for converting storage data of a memory element into a binary code having a plurality of bits each constituted by 0 or 1, and

said detecting/correcting means includes means for detecting/correcting an error on the basis of information data and check data and outputting a data code represented by combinations of data of said plurality of memory elements on the basis of the binary code.

6. A system according to claim 5, further comprising means for generating a binary code corresponding to data to be stored in said plurality of said check memory elements on the basis of the binary code converted from the data code and corresponding to data to be stored in said plurality of said information memory elements to cause said plurality of information memory elements to perform n-value storage on the basis of the binary code.

7. A system according to claim 1, wherein said converting means includes means for converting data such that, when a size of data in said plurality of memory elements changes by one, a binary code of the data has a Hamming distance of 1, for that of the data whose size in said plurality of memory elements is different by one.

8. A system according to claim 1, wherein said plurality of memory elements perform n-value storage using charge amounts stored in said plurality of memory elements and correspond to n data "0", "1", . . . , "n-1" in an order of magnitudes of the charge amounts.

9. A system according to claim 1, wherein said plurality of memory elements is a nonvolatile memory cell obtained by stacking and forming a charge storage layer and a control gate on a semiconductor layer.

10. A system according to claim 1, wherein a storage state of said plurality of memory elements is changed by one.

11. A system according to claim 1, wherein said storing means stores n-bit (2ⁿ <

N^M <

2ⁿ⁺¹) information having a relation n<

2^M using combinations of said M (M;

an integer of not less than

     2) and N-value (N;

an integer of not less than

     3) memory elements.

12. A memory system comprising:

an EEPROM including a plurality of first memory cells each of which stores information data selected from at least three storage states and a plurality of second memory cells each of which stores check data selected from at least three storage states;

a converter for converting the information data stored in said first memory cells and check data stored in said second memory cells into binary codes, respectively, each of said binary codes having a plurality of bits each constituted by 0 or 1;

detecting/correcting means for detecting and correcting an error by using the converted binary codes of the information data and the check data.

13. A memory system according to claim 12, wherein said binary codes including intermediate binary code and said detecting/correcting means for detecting and correcting an error by using the converted intermediate binary codes of the information data and the check data.

14. A memory system comprising:

memory cells each of which stores one of N-levels, where N is an integer of not less than 3;

inverting means for inverting M-sets of an intermediate binary code into data composed of n-bits, where M is an integer of not less than 2 and n is an integer satisfied with a relation of 2ⁿ <

N^M <

2ⁿ⁺¹, and there is one to one correspondence between the intermediate binary code and the N-levels; and

reading means for reading the M-sets of an intermediate binary code from N memory cells.

15. A system according to claim 14, wherein said N-levels correspond to said intermediate binary code such that the difference between the intermediate binary code corresponding to one level and that corresponding to the neighboring level is only one digit.

16. A system according to claim 15, wherein said level is given by a magnitude of charge amounts.

17. A system according to claim 16, wherein said memory cell is obtained by stacking and forming a charge storage layer and control gate on a semiconductor layer.

18. A system according to claim 14, wherein N is 3, M is 2 and n is 3.

19. A system according to claim 14, comprising:

converting means for converting the information data into binary codes including intermediate binary codes which are combinations of binary codes each of which data is stored in one of said plurality of memory cells.

20. A system according to claim 14, wherein said storing means stores the n-value information data by combinations of said plurality of memory cells.

21. A system according to claim 14, wherein said memory cells include information memory cells and check memory cells, comprising:

converting means for causing said check memory cells to generate a binary code corresponding to data to be stored in one of said plurality of memory cells, and

writing means for causing said plurality of memory cells to perform n-value storage on the basis of the binary code.

22. A system according to claim 14, comprising:

converting means for converting data such that, when a size of data in said plurality of memory cells changes by one, a binary code of the data has a Hamming distance of 1, for that of the data whose size in said plurality of memory cells is different by one.

23. A system according to claim 14, wherein said plurality of memory cells perform n-value storage using charge amounts stored in said plurality of memory cells and correspond to n data "0", "1", . . . , "n-1" in an order of magnitudes of the charge amounts.

24. A system according to claim 14, wherein said plurality of memory cells are nonvolatile memory cells obtained by stacking and forcing a charge storage layer and a control gate on a semiconductor layer.

25. A system according to claim 14, wherein a storage state of said plurality of memory cells is changed by one.

26. A system according to claim 14, wherein said memory cells store n-bit (2ⁿ <

N^M <

2ⁿ⁺¹) information having a relation n<

2^M using combinations of said M (M;

an integer of not less than

     2) and N-value (N;

an integer of not less than

     3) memory cells.

27. A system according to claim 14, further comprising error checking and correcting means for checking and correcting data composed of one or plural sets of an intermediate binary code.

28. A system according to claim 27, wherein said N-levels correspond to said intermediate binary code such that the difference between the intermediate binary code corresponding to one level and that corresponding to a neighboring level is only one digit.

29. A system according to claim 28, wherein said level is given by a magnitude of charge amounts.

30. A system according to claim 29, wherein said memory cells are obtained by stacking and forming a charge storage layer and control gate on a semiconductor layer.

31. A system according to claim 27, wherein N is 3, M is 2 and n is 3.

32. A system according to claim 14, further comprising:

converting means for converting data composed of three bits into two sets of an intermediate binary code, in which there is one to one correspondence between the intermediate binary code and the levels;

check data generating means for generating check data from data composed of one or plural sets of an intermediate binary code; and

error checking and correcting means for checking and correcting data composed of one or plural sets of the intermediate binary code.

33. A system according to claim 32, wherein said N-levels correspond to said intermediate binary code such that the difference between the intermediate binary code corresponding to one level and that corresponding to the neighboring level is only one digit.

34. A system according to claim 33, wherein said level is given by a magnitude of charge amounts.

35. A system according to claim 34, wherein said memory cells are obtained by stacking and forming a charge storage layer and control gate on a semiconductor layer.

36. A system according to claim 32, wherein N is 3, M is 2 and n is 3.

37. A memory system comprising:

memory cells each of which stores one of N-levels, where N is an integer of not less than 3;

converting means for converting data composed of n-bits into M-sets of an intermediate binary code, where M is an integer of not less than 2 and n is an integer satisfied with a relation of 2ⁿ <

N^M <

2ⁿ⁺¹, and there is one to one correspondence between the intermediate binary code and the N-levels;

writing means for writing the M-sets of an intermediate binary code into M memory cells;

reading means for reading the M-sets of an intermediate binary code into M memory cells; and

inverting means for inverting the M-sets of an intermediate binary code into the data composed of n-bits.

38. A system according to claim 37, wherein said N-levels correspond to said intermediate binary code such that the difference between the intermediate binary code corresponding to one level and that corresponding to the neighboring level is only one digit.

39. A system according to claim 38, wherein said level is given by a magnitude of charge amounts.

40. A system according to claim 39, wherein said memory cells are obtained by stacking and forming a charge storage layer and control gate on a semiconductor layer.

41. A system according to claim 37, wherein N is 3, M is 2 and n is 3.