Digital storage system adopting semiconductor memory device

• US 5,623,623 A
• Filed: 05/11/1995
• Issued: 04/22/1997
• Est. Priority Date: 09/09/1991
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Suk-ki, Lee, Suk-jung, An, Hyeong-keon, Joo, Tae-sik
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Nguyen, Dzung C.
• Application Number:
  US08/439,070
• Time in Patent Office: 712 Days
• Field of Search: 395/800, 395/700, 395/250, 395/430, 395/888, 395/889, 364/DIG. 1, 364/237.8, 364/260.6
• US Class Current: 711/103
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G11B 20/00007 Time or data compression or expansion audio compression based on psychoacoustics G10L19/00; data processing for reproducing audio data at different playback speeds G10L21/04; video compression H04N19/00; data compression per se H03M7/30
• CPC Class Codes: G11B 20/1813 by adding special bits or symbols to the coded information G11B20/1809 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

A digital data storage system which does not require the use of moving, mechanical components, and which utilizes semiconductor memory elements, thereby improving the reliability and extending the useful life thereof, and also minimizing the cost, complexity, and size thereof relative to conventional digital data storage systems, such as CD players and DAT devices. In a playback only embodiment, the digital data storage system includes a ROM, a system control microcomputer, a digital signal processor (DSP), and a D/A converter. In operation, the DSP is responsive to control signals generated by the system control microcomputer for reading out digital data, e.g., digital audio data, stored in the ROM, and decoding the read-out digital data. The D/A converter functions to convert the decoded read-out digital data into an analog output signal, e.g., an analog audio signal, and to supply the analog output signal to an output terminal. In a record/playback embodiment, the digital data storage system further includes an A/D converter and an EEPROM, to facilitate the recording of digital data. In operation, during a record mode of operation, the A/D converter functions to convert an input analog signal, e.g., an analog audio signal, into an input digital data signal, and the DSP functions, in response to the control signals, to write the input digital data signal into the EEPROM.

Claims

1. A digital data storage system, comprising:

a first semiconductor digital data storage device having an input/output terminal;

a system control microcomputer adapted to generate control signals for controlling operation of said system;

a second semiconductor digital data storage device having a first input/output terminal means and a second input/output terminal means;

a main computer having an input/output terminal means;

a computer interface having a first portion connected to said second input/output terminal means of said second semiconductor digital data storage device and a second portion connected to said input/output terminal means of said main computer;

digital signal processing means having a first input/output terminal means;

memory interface means having a first portion connected to said input/output terminal means of said first semiconductor digital data storage device and a second portion connected to said first input/output terminal means of said digital signal processing means;

wherein said digital signal processing means is responsive to said control signals to selectively execute a playback operation or a record operation;

wherein, during said playback operation, said digital signal processing means functions to read digital data from said first semiconductor digital data storage device via said memory interface means, which functions to buffer said digital data read from said first semiconductor digital data storage device, and further, to transfer said digital data read from said first semiconductor digital data storage device to said second semiconductor digital data storage device;

a memory controller which functions, during said playback operation, to read out said digital data from said second semiconductor digital data storage device to said main computer, via said computer interface, and, during said record operation, functions to control the transfer of digital data to be recorded from said main computer to said second digital data storage device, via said computer interface; and

,

wherein, during said record operation, said digital signal processing means functions to transfer said digital data to be recorded from said second digital data storage device to said first digital data storage device, via said memory interface means, for storage therein.

2. The system as set forth in claim 1, wherein said read-out digital data comprises a digital audio signal.

3. The systems as set forth in claim 1, wherein said first semiconductor digital data storage device comprises at least one EEPROM device.

4. The system as set forth in claim 3, wherein said second semiconductor digital data storage device comprises at least one RAM.

5. The system as set forth in claim 4, wherein said control signals include mode data and sub-code data.

6. The system as set forth in claim 5, further comprising an error corrector, and wherein further, said read-out digital data includes an error correction code embedded therein, and said memory controller functions, in cooperation with said error corrector, during said playback mode of operation, to at least partially decode said error correction code.

7. The system as set forth in claim 6, wherein said memory controller further functions, in cooperation with said error corrector, during said record mode of operation, to encode said digital data to be recorded with an error correction code.

8. The system as set forth in claim 1, wherein said digital signal processing means includes a data compander which functions, during said record mode of operation, to compress said digital data to be recorded, and, during said playback mode of operation, to expand said readout digital data.

9. The system as set forth in claim 8, wherein said digital signal processing means further includes an error correction controller which functions, during said playback mode of operation, to at least partially decode said error correction code.

10. The system as set forth in claim 9, wherein said signal processing means further includes a microcomputer interface connected to said system control microcomputer for receiving said control signals from said system control microcomputer.

11. The system as set forth in claim 10, wherein said digital signal processing means further includes a record/playback controller for generating internal timing signals for synchronizing the processing of said digital data to be recorded and said read-out digital data.

12. The system as set forth in claim 11, wherein said digital signal processing means further includes a RAM interface which functions, during said playback mode of operation, to supply said read-out digital data to said second semiconductor digital data storage device, and, during said record mode of operation, to temporarily store said digital data to be recorded in said memory interface means.

13. The system as set forth in claim 12, wherein said digital signal processing means further includes a digital I/O controller which functions, during said playback mode of operation, to externally output said read-out digital data, and, during said record mode of operation, to receive external digital data to be recorded from an external data source, and to supply said external digital data to be recorded to said first semiconductor digital data storage device for storage therein.

14. The system as set forth in claim 13, wherein said digital I/O controller includes a serial copy management system.

15. The system as set forth in claim 14, wherein said digital signal processing means further includes a timing signal generator for generating timing control signals for synchronizing the operation of said data compander, said error correction controller, said microcomputer interface, said RAM interface, and said digital I/O controller.

16. The system as set forth in claim 15, wherein said external digital data to be recorded comprises a digital audio signal.