Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue

• US 5,623,628 A
• Filed: 03/02/1994
• Issued: 04/22/1997
• Est. Priority Date: 03/02/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hinton, Glenn J., Sarangdhar, Nitin V., Rhodehamel, Michael W., Brayton, James M.
• Primary Examiner(s): Asta, Frank J.
• Application Number:
  US08/205,040
• Time in Patent Office: 1,147 Days
• Field of Search: 395/449, 395/427, 395/444, 395/446, 395/468, 395/473, 395/483, 395/859, 395/861
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency

Abstract

A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

Claims

1. A computer system including:

a bus;

a multi-level memory system coupled to the bus;

a CPU coupled to the bus and to the multi-level memory system, and including,

a cache consistency mechanism for ensuring consistency of data among various level(s) of cache within the multi-level memory system, the cache consistency mechanism including,

an external bus request queue for ensuring that requests to a same address are issued and serviced on the bus according to a predetermined memory ordering scheme, wherein the external bus request queue maintains status information regarding both read and write requests which are to be issued to various levels of the multi-level memory system.

2. The computer system of claim 1 wherein the external bus request queue comprises:

a FIFO for queuing external bus requests.

3. A method of operating a computer system to maintain memory consistency, the computer system including a pipelined external bus, one or more CPUs coupled to the external bus and including an external bus request queue, a memory system including a main memory and one or more levels of cache and coupled to the external bus, the method comprising the steps of:

executing a program on the CPU, the program including a plurality of memory data requests which the program expects will be serviced according to a predetermined ordering, wherein the plurality of memory data requests includes both read and write requests;

issuing the plurality of data requests onto the external bus in a pipelined ordering;

queuing the issued data requests in entries of the external bus request queue to monitor status information regarding each issued data request; and

updating the entries to maintain memory consistency, ensure that each request receives current data, and service requests according to the predetermined ordering.

4. The method of claim 3 wherein the CPU includes a bus agent (DCU, IFU) having L1 cache memory, and wherein:

the issuing step includes the bus agent issuing a request specifying given data and indicating that it has not looked in the L1 cache for the given data; and

the method further includes the step of, responsive to the bus agent indicating that it has not looked in the L1 cache, self-snooping the L1 cache at a later time.

5. The method of claim 4 wherein the external bus request queue includes a FIFO having a start and an end, wherein:

the queuing step includes entering requests at the start of the FIFO;

the updating step includes advancing requests from the start toward the end of the FIFO; and

the method further comprises the steps of,

looking for same address conflicts between a current request in the external bus request queue and a previously issued request which has been entered into the external bus request queue and has passed an L2 cache, and

if a same address conflict is found, blocking the current request by sending it back to the start of the FIFO.

6. An apparatus for use in a computer system having a multi-level memory system, the apparatus comprising:

a cache consistency mechanism for ensuring consistency of data among various level(s) of cache within the multi-level memory system, the cache consistency mechanism including,

an external bus request queue for ensuring that requests to a same address are issued and serviced on the bus according to a predetermined memory ordering scheme, wherein the external bus request queue maintains status information regarding both read and write requests which are to be issued to various levels of the multi-level memory system.

7. The apparatus of claim 6 wherein the external bus request queue comprises:

a FIFO queue for queuing external bus requests.

8. The apparatus of claim 6, further comprising:

a bus agent having an L1 cache memory; and

a self-snooping logic for self-snooping the L1 cache memory at a later time in response to a request received from the bus agent which indicates that it has not looked in the L1 cache memory.

9. The apparatus of claim 6, further comprising:

a control logic, coupled to the external bus request queue, to look for same address conflicts between a current request in the external bus request queue and a previously issued request which has been entered into the external bus request queue and has passed an L2 cache memory; and

blocking logic, coupled to the external bus request queue and the control logic, to block the current request.

10. The apparatus of claim 9, wherein the external bus request queue includes a FIFO queue having a start and an end, and wherein the blocking logic is for blocking the current request by sending the current request to the start of the FIFO queue.

11. An apparatus for use in a computer system to maintain memory consistency, the computer system including a pipelined external bus, one or more CPU'"'"'s coupled to the external bus and including an external bus request queue, a memory system including a main memory and one or more levels of cache memory and coupled to the external bus, the apparatus comprising:

means for executing a program on the CPU, the program including a plurality of data requests which the program expects will be serviced according to a predetermined ordering, wherein the plurality of memory data requests includes both read and write requests;

means for issuing the plurality of data requests onto the external bus in a pipelined ordering;

means for queuing data requests to monitor status information regarding each issued data request; and

means for updating the entries to maintain memory consistency, ensure that each request receives current data, and service requests according to the predetermined ordering.

12. The apparatus of claim 11, wherein the CPU includes a bus agent (DCU,IFU) having L1 cache memory, and wherein:

the means for issuing includes means for the bus agent issuing a request specifying given data and indicating that it has not looked in the L1 cache memory for the given data; and

the apparatus further including means, responsive to the bus agent indicating that it has not looked in the L1 cache memory, for self-snooping the L1 cache memory at a later time.

13. The apparatus of claim 12 wherein:

the means for queuing includes a FIFO having a start and an end;

the means for updating includes means for advancing requests from the start toward the end of the FIFO; and

the apparatus further comprises,

means for entering requests at the start of the FIFO;

means for looking for same address conflicts between a current request in the FIFO and a previously issued request which has been entered into the FIFO and has passed an L2 cache, and

means for blocking, if a same address conflict is found, the current request by sending it back to the start of the FIFO.