Dockable computer system capable of symmetric multi-processing operations

• US 5,625,829 A
• Filed: 07/18/1994
• Issued: 04/29/1997
• Est. Priority Date: 03/25/1994
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Belt, Steven L., Dutton, Drew J., Gephardt, Douglas D.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Nguyen, Dzung C.
• Application Number:
  US08/276,250
• Time in Patent Office: 1,016 Days
• Field of Search: 395/800, 395/325, 395/200, 395/306, 395/308, 395/311, 395/728, 395/827, 364/DIG. 1, 364/242.6, 364/242.92, 364/242.93, 364/180, 364/229
• US Class Current: 710/104
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4036 and deadlock prevention
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004

Abstract

A dockable computer system is capable of performing symmetrical multi-processing operations. More particularly, the dockable computer system includes a portable computer and a host station (docking station), each including a resident CPU. The dockable computer system is capable of operating in a docked state in which the portable computer is physically joined with the host station and an undocked state in which the portable computer is physically separate from the host station. In the docked state, the dockable computer system is capable of performing demanding computational tasks such as video conferencing as one of the CPUs in either the portable computer or host station is dedicated to the video conferencing operation. The dockable computer system preferably includes a communication channel for transmitting multi-processing support signals between the portable computer and the host station. Multi-processing support signals include synchronization signals, cache coherency signals, and interrupt distribution signals such as the LOCK signal, PLOCK signal, FLUSH signal, EADS signal, INTR signal or INTACK signal. The communication channel may be a dedicated bus or may be provided through a docking bridge between the portable computer and host station. The dockable computer system advantageously optimizes CPU resources when the dockable computer system is in a docked state.

Claims

1. A dockable computer system capable of assuming at least two states, a docked state and an undocked state, said dockable computer system comprising:

a host station including a host bus and a general purpose host CPU coupled with said host bus, said host CPU having a host cache;

a portable computer including a computer bus, said host bus capable of electrical communication with said computer bus when said dockable computer system is in said docked state, said host bus being physically separate from said computer bus when said dockable computer system is in said undocked state, said portable computer having a general purpose portable CPU, said portable CPU having a portable cache coupled with said portable bus;

a main memory, said host CPU capable of directly communicating first data to and from said main memory and said host cache when said dockable computer system is in said docked state, and said portable CPU capable of directly communicating second data between said main memory and said portable cache when said dockable computer system is in said docked state, whereby said host CPU and said portable CPU are capable of symmetrical multi-processing operations when said dockable computer system is in said docked state;

a docking bridge; and

a connector bus, said docking bridge being coupled between said connector bus and said portable bus, said docking bridge being intermediate said host bus and said portable bus when said dockable computer system is in said docked state, wherein said docking bridge includes a multi-processing bus for communicating multi-processing support signals between said portable bus and said host bus.

2. The dockable computer system of claim 1, wherein said multi-processing bus is in operative communication with said host CPU and said portable computer when said dockable computer system is in said docked state, said host CPU communicating multi-processing support signals across said multi-processing bus.

3. The dockable computer system of claim 2, wherein said multi-processing support signals are one or more synchronization signals, cache coherency signals or interrupt distribution signals.

4. The dockable computer system of claim 2, wherein said multi-processing support signals include synchronization signals, cache coherency signals and interrupt distribution signals.

5. The dockable computer system of claim 2, wherein said multi-processing support signals include a LOCK signal, a FLUSH signal and an INTR signal.

6. The dockable computer system of claim 2, wherein said multi-processing bus is a dedicated bus.

7. The dockable computer system of claim 6, wherein said multi-processing bus is in operative communication with said main memory and said host CPU when said dockable computer system is in said docked state, wherein said main memory is located in said portable computer.

8. A method of symmetrical multi-processing in a dockable computer system including a memory, a portable computer and a host station, said portable computer having a first general purpose CPU, a portable bus, a connector bus and a docking bridge and said host station having a second general purpose CPU and a host bus, said method comprising the steps of:

performing first processing operations with said first CPU;

simultaneously performing second processing operations with said second CPU; and

transferring symmetrical multi-processing support signals from said host station to said portable computer and from said computer to said host station via said docking bridge, when said host station is docked with said portable computer,

wherein said docking bridge being coupled between said connector bus and said portable bus, said docking bridge being intermediate said host bus and said portable bus when said dockable computer system is in said docked state, wherein said docking bridge includes a multi-processing bus for communicating multi-processing support signals between said portable bus and said host bus.

9. The method of claim 8, wherein said multi-processing bus is a dedicated bus.

10. The method of claim 8, wherein said multi-processing support signals are any two of synchronization signals, cache coherency signals and interrupt distribution signals.

11. The method of claim 10, wherein said multi-processing signals are a LOCK signal, a FLUSH signal and an INTR signal.

12. The method of claim 8, wherein said first CPU is coupled with a first cache and said second CPU is coupled with a second cache, said method further comprising the steps of:

directly transferring first data from said memory to said first cache; and

directly transferring second data from said memory to said second cache.

13. The method of claim 12, wherein said multi-processing bus is a dedicated multi-processing support signal bus coupled to said portable computer and said host station, said dedicated bus including cache control lines.

14. The method of claim 12, further comprising the step of:

transferring said first data from said first cache to said first CPU and simultaneously transferring said second data from said second cache to said second CPU.

15. A computer system comprising:

a main memory;

a main general purpose CPU;

a main bus coupled to said main memory and said main CPU;

a host general purpose CPU;

a host bus coupled to said host CPU; and

an interface coupled to said main bus and said host bus, said host CPU communicating with said main CPU and said main memory across said host bus, said interface and said main bus, said interface including a communication channel for communicating symmetrical multi-processing support signals, wherein said interface includes;

a docking bridge; and

a connector bus, said docking bridge being coupled between said connector bus and said main bus, said docking bridge being intermediate said host bus and said main bus when said dockable computer system is in said docked state, wherein said docking bridge includes a multi-processing bus for communicating multi-processing support signals between said main bus and said host bus.

16. The computer system of claim 15, wherein said multi-processing bus is a dedicated bus.

17. The computer system of claim 15, wherein said communication channel is comprised of dedicated conductors.

18. The computer system of claim 15, wherein said interface is comprised of a host connector coupled to said host bus and a main connector coupled to said main bus, said computer system being in a docked state when said host connector is physically coupled to said main connector and said computer system being in an undocked state when said host connector is physically separate from said main connector.

19. The computer system of claim 18, wherein said communication channel is comprised of dedicated conductors coupled to said main connector and said host connector.

20. In a dockable computer system comprised of a host computer station, including a host general purpose CPU and a station bus, and a mobile computer unit including a general purpose unit CPU and a unit bus, wherein said system is capable of residing in at least two distinct states, a docked state in which said unit is operatively associated with said station and an undocked state in which said unit is physically separate from said station, the improvement comprising:

a dedicated channel circuit in operative communication with said mobile computer unit and said host computer unit when said system is in said docked state for communicating symmetrical multi-processing support signals between said mobile computer unit and said host computer station, wherein said dedicated channel circuit includes;

a docking bridge and a connector bus, said docking bridge being coupled between said connector bus and said unit bus, said docking bridge being intermediate said station bus and said unit bus when said dockable computer system is in said docked state, wherein said docking bridge includes a multi-processing bus for communicating multi-processing support signals between said unit bus and said station bus.

21. The dockable computer system of claim 20, wherein said channel circuit is a dedicated bus including cache control lines.

22. The dockable computer system of claim 20, wherein said multi-processing bus is a dedicated bus.

23. The dockable computer system of claim 22, wherein said docking bridge utilizes a dragon protocol for said multiprocessing support signals.

24. A docking bridge for use in a dockable computer system including a general purpose host CPU coupled to a host bus and a general purpose portable CPU coupled to a portable bus, the docking bridge comprising:

a first bus coupled to said portable bus;

a second bus coupled to said host bus when said system is docked;

a data path circuit including a first buffer and a second buffer coupled between said first bus and said second bus, said data path circuit receiving first data on said first bus and storing said first data in said first buffer for at least one clock cycle and providing said first data on said second bus, said data path circuit receiving second data on said second bus and storing said second data in said second buffer for at least one said clock cycle and providing said second data on said first bus; and

a docking bus arbiter coupled to said first bus and said second bus.

25. The docking bridge of claim 24, further comprising:

a bus lock circuit intermediate said first bus and said second bus, said bus lock circuit receiving synchronization signals on said first bus and providing said synchronization signals on said second bus, said bus lock circuit receiving said bus lock signals from said second bus and providing said bus lock signals on said first bus.

26. The docking bridge of claim 24, further comprising:

downstream interface and upstream interface intermediate said first bus and said second bus, said downstream interface and said upstream interface each including an interrupt cycle forwarding circuit for providing interrupt distribution signals on said first bus and said second bus.

27. The docking bridge of claim 24, wherein the system includes a portable connector coupled to the second bus.

28. The docking bridge of claim 27, wherein the system includes a host connector coupled to the host bus.

29. The docking bridge of claim 24, further comprising:

configuration registers coupled to said first bus and said data path circuit, said configuration registers including control bits for programmably controlling operations of said data path circuit.

30. The docking bridge of claim 29, further comprising:

a cache coherency circuit intermediate said first bus and said second bus, said cache coherency circuit receiving cache coherency signals on said first bus and providing said cache coherency signals on said second bus, said cache coherency circuit receiving said cache coherency signals on said second bus and providing said cache coherency signals on said first bus, said cache coherency circuit providing said cache coherency signals in accordance with a cache coherency protocol.

31. The docking bridge of claim 29, wherein said configuration registers include identification information about components within said dockable computer system.

32. The docking bridge of claim 26, further comprising:

configuration registers wherein said downstream interface and said upstream interface are coupled to said configuration registers, and wherein said configuration registers receive said interrupt distribution signals.