Process of making ESD protection devices for use with antifuses

  • US 5,629,227 A
  • Filed: 04/18/1995
  • Issued: 05/13/1997
  • Est. Priority Date: 07/07/1993
  • Status: Expired due to Fees
First Claim
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1. A process for fabricating an integrated circuit including at least one antifuse and an ESD protection cell for protecting said at least one antifuse from ESD damage during fabrication of said integrated circuit, said process comprising the steps of:

  • a. forming an ESD protection cell lower electrode;

    b. forming a lower electrode for said at least one antifuse;

    c. depositing an interlayer dielectric layer over said ESD protection cell lower electrode and said lower electrode for said at least one antifuse;

    d. opening (i) an ESD protection cell opening having a first areal size and (ii) an antifuse cell opening having substantially said first areal size through said interlayer dielectric layer so as to expose, respectively, (i) a portion of a top surface, a portion of a side surface, and a corner therebetween of said ESD protection cell lower electrode and (ii) said lower electrode of said at least one antifuse;

    e. depositing an antifuse material layer over said interlayer dielectric layer, into said ESD protection cell opening and into said antifuse cell opening so as to overlie said ESD protection cell lower electrode and said lower electrode of said at least one antifuse.

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