Method of fabricating semiconductor light emitting devices

• US 5,629,232 A
• Filed: 11/14/1994
• Issued: 05/13/1997
• Est. Priority Date: 11/14/1994
• Status: Expired due to Fees

• Current Assignee: The Whitaker Corporation (Meggitt PLC)
• Original Assignee: The Whitaker Corporation (Meggitt PLC)
• Inventors: Jiang, Ching-Long
• Primary Examiner(s): Breneman, R. Bruce
• Assistant Examiner(s): Fleck, Linda J.
• Application Number:
  US08/338,991
• Time in Patent Office: 911 Days
• Field of Search: 437/127, 437/129
• US Class Current: 438/40
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/0045 the devices being superluminescent diodes
• CPC Class Codes: H01L 33/641 characterized by the materials

Abstract

Light emitting devices are requiring greater switching speeds to achieve greater modulation bandwidths. The problems of intrinsic capacitance associated with conventional semiconductor heterojunction devices are reduced by the reduction of pn junction capacitance as well as the use of a semi-insulating blocking layer and a conductive substrate. Furthermore, a light absorbing layer is disposed on one side of an unetched portion of the semi-insulating material and an active layer disposed on opposite side. Also, the interface of the semi-insulating material and the active and absorbing layers are at prescribed angles that reduce back reflections to the absorbing and active layers. This arrangement reduces pumping in the absorbing region and thus reduces the lasing effect, allowing for a stable LED. The angle at the interface is determined by having the structure at a predetermined crystallographic direction and having the semi-insulating mesa etched to reveal a predetermined crystalline plane. Finally, in one embodiment of the invention, a channel is etched and filled with thermally conductive material to dissipate heat. This channel, in addition to the heat dissipation effected by the semi-insulating material enables a near linear light output versus current input characteristic for the device.

Claims

1. A process for fabricating a semiconductor light emitting device, comprising the steps of:

(a) Depositing a substrate of InP;

(b) Growing a layer of semi-insulating InP on said substrate;

(c) Selectively masking said semi-insulating layer with an first etchant resistant mask;

(d) Etching said semi-insulating layer and said substrate to reveal a grooves about an unetched portion of said semi-insulating layer and removing said first mask thereafter;

(e) Depositing successive layers of a first InP cladding layer, InGaAsP active layer, a second InP cladding layer and a conductive cap layer;

(f) Masking said cap layer selectively with a second etchant resistant mask;

(g) Etching said cap layer, said second cladding layer, and said active layer to reveal a channel in a selected first region of said device and to remove a selected portions of said cap layer and said second cladding layer in a selected second region of said device and removing said second mask; and

(h) Depositing a layer of thermally conducting material in said channel and on said cap layer in said selected first region of said device.

2. A process as recited in claim 1, wherein said substrate is n-doped, and said cap layer is p-doped.

3. A process as recited in claim 1, wherein said semi-insulating layer is doped with Fe or Co.

4. A process as recited in claim 1 wherein said semi-insulating layer and said substrate layer are monocrystalline materials and said etching reveals planes in preferred crystallographic orientations.

5. A process as recited in claim 1 wherein said semi-insulating layer is etched at an angle relative to said substrate and said active layer.

6. A process as recited in claim 4, wherein said substrate is a (100) crystal and said semi-insulating layer is etched to reveal the (111) crystalline plane.

7. A process for fabricating a semiconductor light emitting device, comprising the steps of:

(a) Depositing a substrate of InP;

(b) Growing a layer of semi-insulating InP on said substrate;

(c) Selectively masking said semi-insulating layer with a first etchant resistant mask;

(d) Etching said semi-insulating layer and said substrate to grooves about an unetched portion of said semi-insulating layer and removing said first mask thereafter;

(e) Depositing successive layers of a first InP cladding layer, InGaAsP active layer, a second InP cladding layer and a conductive cap layer;

(f) Masking said cap layer selectively with a second etchant resistant mask; and

(g) Etching said to remove selected portions of said cap layer and said second cladding layer in a selected second region of said device leaving said cap, cladding layers, said substrate and said substrate in a selected first region of said device and removing said second mask.

8. A process as recited in claim 7, wherein said active layer in said second region acts as an optically absorbing layer.

9. A process as recited in claim 7, wherein said semi-insulating layer is doped with Fe or Co.

10. A process as recited in claim 7, wherein said semi-insulating layer and said substrate layer are monocrystalline materials and said etching reveals planes in preferred crystallographic orientations.

11. A process as recited in claim 7, wherein said semi-insulating layer is etched at an angle relative to said substrate and said active layer, said angle chosen to reduce back reflection to said active layer.

12. A process as recited in claim 10, wherein said substrate is a (100) crystal and said semi-insulating layer is etched to reveal the (111) crystalline plane.