Disk emulation for a non-volatile semiconductor memory utilizing a mapping table

• US 5,630,093 A
• Filed: 04/19/1996
• Issued: 05/13/1997
• Est. Priority Date: 12/31/1990
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Robinson, Kurt B., Holzhammer, Gerald S.
• Primary Examiner(s): Lane, Jack A.
• Assistant Examiner(s): Verbrugge, Kevin
• Application Number:
  US08/635,030
• Time in Patent Office: 389 Days
• Field of Search: 395/182.05, 395/182.06, 395/442, 395/412, 395/421.11, 395/600, 395/430
• US Class Current: 711/115
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system

Abstract

A non-volatile semiconductor memory that is erased in blocks is described. The non-volatile semiconductor memory includes an active block for storing first data and a reserve block for storing second data. The second data is a copy of the first data. The copy is made during a clean-up operation prior to erasure of the active block. The non-volatile semiconductor memory also includes a mapping table for mapping a logical address of an allocation unit to a physical address of a sector within the non-volatile semiconductor memory.

Claims

1. A non-volatile semiconductor memory system that emulates a disk storage device comprising at least one allocation unit, each allocation unit comprising at least one sector, said non-volatile semiconductor memory system comprising non-volatile semiconductor memory comprising a plurality of blocks, wherein said memory is erased in blocks, each of said blocks comprising a plurality of sectors, said system comprising:

(A) an active block for storing first data;

(B) a reserve block for storing second data, wherein the second data is a copy of the first data, wherein the copy is made during a clean-up operation prior to an erasure of the active block;

(C) a mapping table for mapping a logical address of an allocation unit of a disk storage device to a physical address of a sector within the non-volatile semiconductor memory, said mapping table comprising;

(1) at least one logical address field corresponding to a logical address of an allocation unit on a disk storage device emulated,

(2) a first corresponding physical address field of a sector within the non-volatile semiconductor memory,

(3) a next logical address field comprising a first value if the first corresponding physical address is clean such that valid data is located in the non-volatile semiconductor memory at that first physical address, said next logical address comprising a logical address value pointing to a second logical address and corresponding second physical address in the mapping table if said first physical address is dirty such that invalid data is located at the first physical address, and

said mapping table being updated during a clean-up operation to change the first value of the next logical address field to point to the second logical address and to update the corresponding physical address to identify the second physical address, the second physical address being an address of the data copied into the reserve block in the non-volatile semiconductor memory.

2. The non-volatile semiconductor memory of claim 1, wherein the computer memory is a flash electrically erasable programmable read-only memory.

3. The non-volatile semiconductor memory of claim 1, further comprising:

(D) a block status table for providing information as to whether a block of the non-volatile semiconductor memory is;

(1) an active or a reserve block,

(2) free or in use, and

(3) defective or not defective.

4. The non-volatile semiconductor memory of claim 3, wherein at least one block comprises:

(E) a header containing information comprising;

(1) an unformatted size of the non-volatile semiconductor memory;

(2) a maximum number of erase cycles recommended for the non-volatile semiconductor memory;

(3) identification of values of erase and write voltages;

(4) identification of erase and write commands that are issued to respectively execute erase and write algorithms;

(5) erase and write algorithms.

5. The non-volatile semiconductor memory of claim 1, wherein the allocation unit is a sector.

6. The non-volatile semiconductor memory of claim 1, wherein the allocation unit is a cluster comprising a plurality of sectors.

7. The non-volatile semiconductor memory of claim 1, further comprising an inverter for logically inverting each bit of data read from the non-volatile semiconductor memory.

8. The non-volatile semiconductor memory of claim 1, further comprising a block containing an error correction code data field.

9. The non-volatile semiconductor memory of claim 1, further comprising a block containing a sector allocation bitmap.

18. The non-volatile semiconductor memory of claim 1, wherein previous data at a determined logical address is modified by writing modified data to a free address in the non-volatile semiconductor memory, adding a new entry into the mapping table comprising a logical address field and corresponding physical address field and next logical address field to identify the physical address the modified data was written to and to set the next logical address field to the first value, and changing the corresponding next logical address field of the previous data from the first value to a value which points to the logical address of the new entry.

23. The non-volatile semiconductor memory as set forth in claim 1, wherein the first value is a null value.

10. A computer system comprising:

(A) a central processing unit;

(B) a non-volatile semiconductor memory system that emulates a disk storage device comprising at least one allocation unit, each allocation unit comprising at least one sector, said non-volatile semiconductor memory system comprising non-volatile semiconductor memory comprising a plurality of blocks, wherein said memory is erasable in blocks, each of said blocks comprising a plurality of sectors, wherein the non-volatile semiconductor memory is accessed by the central processing unit, and wherein the non-volatile memory comprises;

(1) an active block for storing first data;

(2) a reserve block for storing second data, wherein the second data is a copy of the first data, wherein the copy is made during a clean-up operation prior to an erasure of the active block;

(3) a mapping table for mapping a logical address of an allocation unit of a disk storage device to a physical address of a sector within the non-volatile semiconductor memory, said mapping table comprising;

(a) at least one logical address field corresponding to a logical address of an allocation unit on a disk storage device emulated,

(b) a first corresponding physical address field of a sector within the non-volatile semiconductor memory,

(c) a next logical address field comprising a first value if the first corresponding physical address is clean such that valid data is located in the non-volatile semiconductor memory at that first physical address, said next logical address comprising a logical address value pointing to a second logical address and corresponding second physical address in the mapping table if said first physical address is dirty such that invalid data is located at the first physical address, and

said mapping table being updated during a clean-up operation to change the first value of the next logical address field to point to the second logical address and to update the corresponding physical address to identify the second physical address, the second physical address being an address of the data copied into the reserve block in the non-volatile semiconductor memory such that a disk storage device is emulated and the mapping table performs translations to perform the emulation; and

(C) storage means for storing code for controlling the non-volatile memory.

11. The computer system of claim 10, wherein the storage means is a read-only memory.

12. The computer system of claim 10 wherein the storage means is a random-access memory.

13. The computer system of claim 12, wherein the random-access memory is a general-purpose system random-access memory.

14. The computer system of claim 12, wherein the random-access memory is a buffer memory.

15. The computer system of claim 10, wherein the non-volatile semiconductor memory is paged-memory mapped.

16. The computer system of claim 10, wherein the non-volatile semiconductor memory is direct memory mapped.

17. The computer system of claim 10, further comprising a hardware controller for executing the code for controlling the non-volatile semiconductor memory.

19. The computer system of claim 10, wherein previous data at a determined logical address is modified by writing modified data to a free address in the non-volatile semiconductor memory, adding a new entry into the mapping table comprising a logical address field and corresponding physical address field and next logical address field to identify the physical address the modified data was written to and to set the next logical address field to the first value, and changing the corresponding next logical address field of the previous data from the first value to a value which points to the logical address of the new entry.

24. The computer system as set forth in claim 10, wherein the first value is a null value.

20. In a non-volatile semiconductor memory comprising a plurality of blocks, a method for emulating a disk storage device comprising at least one allocation unit, each allocation unit comprising at least one sector, said method comprising the steps of:

(A) providing a mapping table comprising at least one entry that maps a logical address for accessing the disk storage device to a physical address of the semiconductor memory, each entry including a logical address field corresponding to a logical address of an allocation unit on a disk storage device emulated, a first corresponding physical address field of a sector within the non-volatile semiconductor memory, and a next logical address field comprising a first value if the first corresponding physical address is clean such that valid data is located in the non-volatile semiconductor memory at that first physical address, said next logical address comprising a logical address value pointing to another logical address and another corresponding physical address in the mapping table if said first physical address is dirty such that invalid data is located at the first physical address;

(B) generating a linked list of entries for each logical address corresponding to a given logical address of an allocation unit on a disk storage device emulated, said linked list added to each time data is moved in the non-volatile semiconductor memory, said next logical address field pointing to a next logical address entry in the table, the next logical address field of a last entry containing a first value to indicate the end of the linked list and that valid data is located in the memory at the corresponding physical address;

(C) updating data by writing new data to a free memory location, adding a new entry at an available logical address to the linked list to identify the physical address at which the new data is located, said corresponding next logical address field being set to the first value to identify a new last entry in the linked list and the location of the valid data, and updating the next logical address field of a prior last entry in the linked list from the first value to a value which points to the logical address in the table at which the new entry is located.

21. The method as set forth in claim 20 wherein the memory is erased in blocks, said method further comprising the steps of:

(D) providing an active block for storing first data;

(E) providing a reserve block for storing second data;

(F) performing an erasure of a block comprising the steps of;

(1) performing a clean-up operation of the block to be erased by copying said first data to the reserve block as the second data;

(2) updating the mapping table to change the first value of the next logical address field to point to an available next logical address and updating the corresponding physical address to the next logical address to identify the physical address of the data copied into the reserve block in the non-volatile semiconductor memory; and

(3) erasing said block.

25. The method as set forth in claim 20, wherein the first value is a null value.

22. A non-volatile semiconductor memory system that emulates a disk storage device comprising at least one allocation unit, each allocation unit comprising at least one sector, said non-volatile semiconductor memory system comprising non-volatile semiconductor memory comprising a plurality of blocks, each of said blocks comprising a plurality of sectors, said system comprising:

(A) a mapping table for mapping logical addresses of an allocation unit of a disk storage device to physical addresses of a sector within the non-volatile semiconductor memory, said mapping table comprising;

(1) at least one logical address field corresponding to a logical address of an allocation unit on a disk storage device emulated; and

(2) a first corresponding physical address field of a sector within the non-volatile semiconductor memory;

(B) a read/write controller for performing read and write operations to the non-volatile semiconductor memory, said controller performing a read operation by referencing the mapping table for translating the logical address to be accessed to the corresponding physical address in the non-volatile semiconductor memory, said controller performing a write operation by writing the data to a free memory location identified by a different physical address, said controller updating the mapping table to identify the different physical address;

wherein memory write operations are performed in a timely manner without performing a prior erasure operation to emulate a disk storage device.

26. The non-volatile semiconductor memory system as set forth in claim 22, wherein the first value is a null value.