Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order

  • US 5,630,096 A
  • Filed: 05/10/1995
  • Issued: 05/13/1997
  • Est. Priority Date: 05/10/1995
  • Status: Expired due to Term
First Claim
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1. A controller for a synchronous DRAM comprising:

  • a sorting unit for receiving memory requests and sorting said memory requests based on their addresses, wherein said memory requests are tagged for indicating a sending order thereof before said memory requests are sent to said sorting unit;

    a throughput maximizing unit for processing said memory requests to the synchronous DRAM in response to scheduling which maximizes the use of data slots by the synchronous DRAM.

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