System using timing information contained in data read from reproduction unit controlled by first oscillator to vary frequency of independent system clock signal

• US 5,630,112 A
• Filed: 09/06/1994
• Issued: 05/13/1997
• Est. Priority Date: 06/19/1991
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Uchida, Takayuki, Yoshida, Takuji
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Nahm, Sang Y.
• Application Number:
  US08/301,266
• Time in Patent Office: 980 Days
• Field of Search: 84/601, 84/605, 84/648, 84/671, 84/672, 84/673, 84/674, 84/675, 395/250, 370/102, 370/108, 375/372
• US Class Current: 713/501
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

The present invention relates to a digital data processing apparatus for transferring digital data which is output from a disc reproduction section (15₁) to a buffer memory (18)-equipped host processing section (13) and for making processing. By detecting a shift in frequency of an operation clock on the basis of an output of the disc reproduction section (15₁) and varying the frequency of the operation clock of the host processing section (13) in accordance with a result of that detection, it is possible to prevent the memory (18) from being placed in an over- or an underflowed state and to perform a normal data reproduction.

Claims

1. A digital data processing apparatus comprising:

a reproduction section for reproducing and outputting based on a first clock signal generated by a first clock generation circuit, digital data which is stored on a recording medium, wherein the first clock generating circuit has a first oscillator means;

a host processing section for performing predetermined processing, the host processing section having a memory for storing the digital data that is outputted by the reproduction section and for outputting the digital data stored in the memory in accordance with a second clock signal generated by a second clock generating circuit, wherein the second clock generating circuit has a second oscillator means and the second oscillator means is physically different from the first oscillator means; and

control means for detecting a shift in a frequency of the first clock signal based on a specific timing reference component contained in the digital data that is outputted by the reproduction section and for varying a frequency of the second clock signal in accordance with the detected shift in the frequency of the first clock signal.

2. A digital data processing apparatus according to claim 1, wherein the control means varies the frequency of the second clock signal in accordance with the detected shift in the frequency of the first clock signal so that a speed of the digital data outputted from the memory is the same as a speed in which the digital data is stored in the memory.

3. A digital data processing apparatus according to claim 1, wherein:

the digital data is divided into blocks; and

the control means includes;

detecting means for detecting a specific signal component of each block;

counting means for counting the second clock signal and for generating a timing signal that has a cycle that corresponds to the blocks;

comparing means for comparing the timing signal and the detected specific signal components; and

adjusting means, responsive to the comparison made by the comparing means, for varying the frequency of the second clock signal.

4. A digital data processing apparatus according to claim 3, wherein the detected specific signal component of each block includes a synchronizing signal.

5. A digital data processing apparatus according to claim 3, wherein the detected specific signal component of each block includes a signal that corresponds to a head position of the block.

6. A digital data processing apparatus comprising:

a reproduction section for reproducing and outputting, based on a first clock signal generated by a first clock generation circuit, digital data which is stored on a recording medium, wherein the digital data is divided into blocks;

a host processing section for performing predetermined processing, the host processing section having a memory for storing the digital data that is outputted by the reproduction section and for outputting the digital data stored in the memory in accordance with a second clock signal generated by a second clock generating circuit; and

control means for detecting a shift in a frequency of the first clock signal in accordance with the digital data that is outputted by the reproduction section and for varying a frequency of the second clock signal in accordance with the detected shift in the frequency of the first clock signal, wherein the control means includes;

detecting means for detecting a specific signal component of each block;

counting means for counting the second clock signal and for generating a timing signal that has a cycle that corresponds to the blocks;

comparing means for comparing the timing signal and the detected specific signal components; and

adjusting means, responsive to the comparison made by the comparing means, for varying the frequency of the second clock signal.

7. A digital data processing apparatus according to claim 6, wherein the detected specific signal component of each block includes a synchronizing signal.

8. A digital data processing apparatus according to claim 6, wherein the detected specific signal component of each block includes a signal that corresponds to a head position of the block.

9. A digital data processing apparatus for processing digital audio data comprising:

a reproduction section including;

a first clock generation circuit, including a first crystal oscillator, for generating a first clock signal; and

reproducing means for reproducing and outputting, based on the first clock signal, the digital audio data which is stored on a disc type recording medium;

a host processing section for performing predetermined processing, the host processing section including;

a second clock generating circuit, including a second crystal oscillator, for generating a second clock signal, wherein the second crystal oscillator is physically different from the first crystal oscillator; and

a memory for storing the digital audio data that is outputted by the reproducing means and for outputting the digital audio data stored in the memory in accordance with the second clock signal; and

control means for detecting, based on a specific timing reference component contained in the digital audio data that is outputted by the reproducing means, a shift in a frequency of the first clock signal, and for varying, in accordance with the detected shift in the frequency of the first clock signal, a frequency of the second clock signal.

10. A digital data processing apparatus comprising:

a reproduction section for reproducing and outputting, based on a first clock signal generated by a first clock generation circuit, digital data which is divided into blocks and which is stored on a recording medium, wherein the first clock generating circuit has a first oscillator means;

a host processing section for performing predetermined processing, the host processing section having a memory for storing the digital data that is outputted by the reproduction section and for outputting the digital data stored in the memory in accordance with a second clock signal generated by a second clock generating circuit, wherein the second clock generating circuit has a second oscillator means and the second oscillator means is physically different from the first oscillator means; and

control means for detecting a shift in a frequency of the first clock signal in accordance with the digital data that is outputted by the reproduction section and for varying a frequency of the second clock signal in accordance with the detected shift in the frequency of the first clock signal, the control means including;

detecting means for detecting a specific signal component of each block;

counting means for counting the second clock signal and for generating a timing signal that has a cycle that corresponds to the blocks;

comparing means for comparing the timing signal and the detected specific signal components; and

adjusting means, responsive to the comparison made by the comparing means, for varying the frequency of the second clock signal.

11. A digital data processing apparatus according to claim 10, wherein the detected specific signal component of each block includes a synchronizing signal.

12. A digital data processing apparatus according to claim 10, wherein the detected specific signal component of each block includes a signal that corresponds to a head position of the block.