Accelerometer-based shock/vibration testing apparatus and associated methods for a portable computer

• US 5,631,427 A
• Filed: 01/16/1996
• Issued: 05/20/1997
• Est. Priority Date: 01/16/1996
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Bridges, John W.
• Primary Examiner(s): Williams, Hezron E.
• Assistant Examiner(s): MOLLER, RICHARD ALAN
• Application Number:
  US08/587,261
• Time in Patent Office: 490 Days
• Field of Search: 73/658, 73/489, 73/491, 73/509, 73/654, 73/493, 73/514.32, 340/669, 340/683, 340/693, 340/429, 340/636, 340/566, 307/64, 307/66, 364/551.01, 364/566
• US Class Current: 73/658
• CPC Class Codes: G01D 9/005 Solid-state data loggers
• CPC Class Codes: G01P 1/127 for acceleration values
• CPC Class Codes: G07C 3/04 using counting means or digital clocks

Abstract

A portable notebook computer has a shock/vibration testing system incorporated therein and including first and second memory chips and a miniature accelerometer mounted on the computer motherboard and interconnected to the power supply board and storage battery portions of the computer by a power supply switchover circuit. During operational periods of the computer the switchover circuit connects the power supply board output to the accelerometer input, and the accelerometer output to the first memory chip, so that accelerometer output data indicative of the operational shock/vibration loads borne by the computer is received and stored in the first memory chip. During non-operational periods of the computer the switchover circuit connects the storage battery output to the accelerometer input, and the accelerometer output to the second memory chip, so that accelerometer output data indicative of the non-operational shock/vibration loads borne by the computer is received and stored in the second memory chip. After a predetermined test period the operational and non-operational shock/vibration loading data stored in the two memory chips is retrieved and analyzed by suitable diagnostic software loaded in the computer.

Claims

1. Computer apparatus comprising:

a computer having a first power supply structure with an output from which electrical power from said first power supply structure may be transmitted during operational periods of the computer, and a second power supply structure with an output from which electrical power from said second power supply structure may be transmitted during non-operational periods of the computer;

an accelerometer carried by said computer and operative to sense shock and vibration loads to which said computer is subjected during said operational and non-operational periods thereof, said accelerometer having an electrical power supply input and an electrical measurement signal output;

first and second memory means carried by said computer and operative to separately receive and store shock and vibration load data for subsequent retrieval; and

switchover circuitry operative to automatically;

(1) couple said first power supply structure output to said accelerometer electrical power supply input, and to couple said accelerometer electrical measurement signal output to said first memory means, during said operational periods of said computer, and

(2) couple said second power supply structure to said accelerometer electrical power supply input, and to couple said accelerometer electrical measurement signal output to said second memory means, during said non-operational periods of said computer.

2. The computer apparatus of claim 1 wherein said computer is a notebook computer.

3. The computer apparatus of claim 1 wherein:

said computer further has a circuit board therein, and

said accelerometer and said first and second memory means are operatively mounted on said circuit board.

4. The computer apparatus of claim 3 wherein:

said first and second memory means are separate memory chips.

5. The computer apparatus of claim 3 wherein:

said circuit board is a computer system motherboard.

6. The computer apparatus of claim 1 wherein:

said first power supply structure is a power supply board operative, during said operational periods of said computer, to receive AC electrical power from a source thereof and responsively transmit DC electrical power from said output of said first power supply structure, and

said second power supply structure is a DC storage battery.

7. The computer apparatus of claim 1 further comprising:

diagnostic software loaded into said computer and operative to retrieve and analyze shock and vibrational load data stored in said first and second memory means.

8. The computer apparatus of claim 1 wherein said switchover circuitry includes:

a first two-position electrical switching relay powered by said first power supply structure and operatively interconnecting said accelerometer electrical measurement signal output and said first and second memory means, and

a second two-position electrical switching relay powered by said first power supply structure and operatively interconnecting said accelerometer power supply input, said first power supply structure output, and said second power supply structure output.

9. For use in conjunction with a computer having first and second power supply structures with outputs from which electrical power may be transmitted respectively during operational and non-operational periods of the computer, a method of determining the shock and vibration loading to which the computer is subjected during such operational and non-operational periods, said method comprising the steps of:

positioning an accelerometer and first and second memory means in the computer;

electrically powering said accelerometer using the first power supply structure, and enabling said accelerometer to transmit sensed shock/vibration load data to said first memory means for storage therein, in response to transmission of electrical power from said output of said first power supply structure; and

electrically powering said accelerometer using the second power supply structure, and enabling said accelerometer to transmit sensed shock/vibration load data to said second memory means for storage therein, in response to cessation of transmission of electrical power from said output of said first power supply structure.

10. The method of claim 9 wherein:

the computer has a circuit board therein, and

said positioning step is performed by operatively mounting said accelerometer, and said first and second memory means, on said circuit board.

11. The method of claim 10 wherein:

the computer has a system motherboard therein, and

said positioning step includes the step of operatively mounting said accelerometer, and first and second separate memory chips, on said system motherboard.

12. The method of claim 9 wherein said accelerometer has an electrical power supply input and an electrical measurement signal output, and said electrically powering and enabling steps include the steps of:

connecting the electrical power inputs of first and second electrical switching relays to said first power supply structure,

using said first relay to operatively couple said electrical measurement signal output of said accelerometer to a selectively variable one of said first and second memory means, and

using said second relay to operatively couple the output of a selectively variable one of said first and second power supply structures to said power supply input of said accelerometer.

13. The method of claim 9 further comprising the step of:

retrieving and analyzing shock and vibrational load data generated by said accelerometer and stored in said first and second memory means.

14. The method of claim 13 wherein:

said retrieving and analyzing step is performed using a diagnostic software program installed in said computer and operatively coupled to said first and second memory devices.

15. Computer apparatus comprising:

a computer having disposed therein a circuit board, an AC-to-DC power board with an output from which electrical power may be generated during operational periods of the computer, and a DC storage battery with an output from which electrical power may be generated during non-operational periods of the computer;

an accelerometer mounted on said circuit board and operative to sense shock and vibration loads to which said computer is subjected during said operational and non-operational periods thereof, said accelerometer having an electrical power supply input and an electrical measurement signal output;

first and second memory chips mounted on said circuit board and operative to receive and store shock and vibration load data for subsequent retrieval; and

switchover circuitry operative to automatically;

(1) couple said power supply board output to said accelerometer electrical power supply input, and to couple said accelerometer electrical measurement signal output to said first memory chip, during said operational periods of said computer, and

(2) couple said DC storage battery output to said accelerometer electrical power supply input, and to couple said accelerometer electrical measurement signal output to said second memory chip, during said non-operational periods of said computer, said switchover circuitry including;

a first two-position electrical switching relay powered by said power supply board and operatively interconnecting said accelerometer electrical measurement signal output and said first and second memory chips, and

a second two-position electrical switching relay powered by said power supply board and operatively interconnecting said accelerometer power supply input, said power supply board, and said DC storage battery.

16. The computer apparatus of claim 15 wherein:

said computer is a portable computer.

17. The computer apparatus of claim 16 wherein:

said portable computer is a notebook computer.

18. The computer apparatus of claim 15 wherein:

said circuit board is a system motherboard.

19. The computer apparatus of claim 15 further comprising:

diagnostic software loaded into said computer and operative to retrieve and analyze shock and vibrational data stored in said first and second memory chips.