Synchronous dual port RAM

• US 5,631,577 A
• Filed: 06/21/1996
• Issued: 05/20/1997
• Est. Priority Date: 02/10/1995
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Syu, Tsung-Lu, Erickson, Charles R., Freidin, Philip M., Cheung, Edmond Y.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/668,276
• Time in Patent Office: 333 Days
• Field of Search: 326/39, 326/40, 326/46, 365/230.05
• US Class Current: 326/40
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns

Abstract

A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.

Claims

1. A structure for a programmable logic device comprising:

a first logic generator having a Read Address terminal and a Write Address Terminal;

a second logic generator having a Read Address terminal and a Write Address Terminal;

addressing circuitry coupled to said Read and Write Address terminals of said first and second logic generators, wherein a control signal provided to said addressing circuitry provides a signal to the Write Address terminals of said first and second logic generators.

2. The structure of claim 1 wherein said addressing circuitry includes a multiplexer which selectively provides said signal.

3. The structure of claim 2 wherein said addressing circuitry further includes a first latch coupled between said multiplexer and said Write Address terminal of said first logic generator.

4. The structure of claim 3 wherein said addressing circuitry further includes a second latch coupled between said addressing circuitry and said Write Address terminal of said second logic generator.

5. The structure of claim 2 wherein said addressing circuitry includes a first address decoder for providing a first input signal to said multiplexer and said Read Address terminal of said first logic generator.

6. The structure of claim 5 wherein said addressing circuitry includes a second address decoder for providing a second input signal to said multiplexer and said Read Address terminal of said second logic generator.

7. A configurable logic block configuration comprising:

a first set of random access memory cells;

a second set of random access memory cells;

first addressing means for providing a first Read address signal to address one of said first set of random access memory cells;

second addressing means for providing a second Read address signal to address one of said second set of random access memory cells; and

means for selectively providing said first Read signal or said second Read address signal to write to one of said first set of random access memory cells.

8. The configurable logic block of claim 7 wherein said means for selectively providing includes a multiplexer.

9. The configurable logic block of claim 8 wherein said first addressing means includes an address decode circuit coupled to an input terminal of said multiplexer.

10. The configurable logic block of claim 8 wherein said second addressing means includes an address decode circuit coupled to an input terminal of said multiplexer.