Reduced area word line driving circuit for random access memory

  • US 5,633,832 A
  • Filed: 09/26/1995
  • Issued: 05/27/1997
  • Est. Priority Date: 09/26/1995
  • Status: Expired due to Term
First Claim
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1. In a semiconductor memory device having a first power supply voltage, a second power supply voltage, and a boost power supply voltage greater than the first power supply voltage, a word line driving circuit, comprising:

  • a decoder circuit including a select circuit having a number of active devices coupled between a decode node and the second power supply, the select circuit pulling the control node to the second power supply in response to a plurality of active decoder signals in a select operation, the decoder circuit further including a deselect circuit coupled between the first power supply and the control node, the deselect circuit pulling the control node to the first power supply in response to an active reset signal in a deselect operation; and

    a plurality of word line driver stages, each said stage including,a transfer transistor coupled between the decode node and a control node and responsive to word line select signal, the transfer transistor coupling the first power supply voltage to its respective control node in the deselect operation,a first driver transistor of a first conductivity type having its source coupled to the boost voltage, its drain coupled to a word line, and its gate coupled to a control node,a second driver transistor of a second conductivity type having its source coupled to the second power supply voltage, its drain coupled to the word line, and its gate coupled the control node, anda level shifting transistor of the first conductivity type having its source coupled to the boost voltage, its drain coupled to the control node, and its gate coupled to the word line.

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