Low cell charge enable circuit

• US 5,635,821 A
• Filed: 06/30/1995
• Issued: 06/03/1997
• Est. Priority Date: 06/30/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Smith, Gregory J.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): SHIN, KYUNG E
• Application Number:
  US08/497,575
• Time in Patent Office: 704 Days
• Field of Search: 320/40, 320/49, 320/54, 320/5, 320/15
• US Class Current: 320/103
• CPC Class Codes: H02J 7/0031 using battery or load disconnect circuits H02J9/002 takes precedence
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration

Abstract

A circuit and method of operating a circuit furnish a capability to connect a battery in a conduction mode to a battery pack and, therefore, to a charger. The circuit and method furnish this capability even when no power is available for driving normally active electronic circuits. The circuit includes passive-type components which sense for the presence of a charger and activate switches for connecting the battery to the charger. The circuit and method in these embodiments supply this capability by applying a voltage derived from the charger to a power switch connecting the battery to the battery pack. For example, for a battery pack utilizing a power switch including two power FETs connected back-to-back, the circuit pulls a gate potential of the power switch FETs as far as possible from the potential at the minus terminal of the power pack so that conduction through the FETs and battery accompanies attachment of the charger to the battery pack.

Claims

1. A circuit for charging a deeply discharged battery cell comprising:

a power switch having a control terminal, the power switch for coupling to the cell;

plus and minus battery pack terminals for coupling across the series-connected power switch and cell and for coupling to a charger or a load;

a transistor having a current path coupled between the plus terminal and the power switch control terminal and having a control terminal coupled to the minus terminal; and

a resistor coupled between the transistor control terminal and the minus terminal.

2. A circuit according to claim 1 wherein the power switch further comprises:

a power FET having a drain for coupling to the cell in series, a source and a gate; and

a resistor coupled between the power FET source and gate.

3. A circuit according to claim 1 wherein the power switch further comprises:

a first and a second power FET coupled back-to-back in series at a common drain node;

a first resistor coupled between the source and gate of the first power FET; and

a second resistor coupled between the source and gate of the second power FET.

4. A circuit according to claim 1 wherein the power switch further comprises:

two power FETs coupled back-to-back in series at a common source node and a common gate node, the common gate node being the control terminal; and

a resistor coupled between the common source node and the common gate node.

5. A switch according to claim 4 wherein the two power FETs include:

a first N-channel MOSFET having a source terminal coupled to a first end of the resistor, a drain terminal and a gate terminal coupled to the second end of the resistor; and

a second N-channel MOSFET having a source terminal coupled to the source terminal of the first N-channel MOSFET and coupled to the first end of the resistor, a drain terminal and a gate terminal coupled to the gate terminal of the first N-channel MOSFET and to the second end of the resistor.

6. A circuit according to claim 1 further comprising:

a capacitor coupled in series with the resistor between the transistor control terminal and the minus terminal.

7. A circuit according to claim 1 wherein the transistor is a first transistor, further comprising:

a second transistor having a current path coupled between the first transistor control terminal and the minus terminal.

8. A circuit according to claim 7 wherein:

the first transistor is a bipolar PNP transistor having an emitter coupled to the plus terminal, a collector coupled to the power switch control terminal and a base; and

the second transistor is a bipolar NPN transistor having a collector coupled to the first transistor base, an emitter coupled to the minus terminal and a base coupled to a ground reference.

9. A circuit according to claim 7 wherein:

the first transistor is a high voltage transistor.

10. A circuit according to claim 7 further comprising:

a switch alternatively disconnecting and connecting the control terminal of the first transistor and the current path of the second transistor to the plus terminal.

11. A circuit according to claim 7 further comprising:

a diode coupled in the current path between the first transistor control terminal and the second transistor.

12. A circuit according to claim 1 wherein the circuit charges a deeply discharged battery cell of a plurality of battery cells in a battery stack.

13. A circuit according to claim 1 further comprising:

a controller having a control terminal coupled to the power switch control terminal to control the power switch.

14. A circuit according to claim 13 wherein the controller further comprises:

a high voltage bipolar junction transistor (BJT) coupled to the power switch control terminal; and

a switch coupling the plus terminal to the high voltage FET.

15. A circuit according to claim 13 wherein the controller further comprises:

a high voltage FET coupled to the power switch control terminal; and

a switch coupling the plus terminal to the high voltage FET.

16. A circuit according to claim 15 wherein the high voltage FET comprises:

a PMOS FET having a source coupled to the plus terminal, a drain coupled to the power switch control terminal and a gate coupled to a node between the power switch and the cell.

17. A circuit according to claim 13 wherein the power switch further comprises:

two power FETs coupled hack-to-back in series at a common source node and a common gate node, the common gate node being the control terminal; and

a resistor coupled between the common source node and the common gate node.

18. A circuit according to claim 17 wherein the two power FETs include:

a first N-channel MOSFET having a source terminal coupled to a first end of the resistor, a drain terminal and a gate terminal coupled to the second end of the resistor; and

a second N-channel MOSFET having a source terminal coupled to the source terminal of the first N-channel MOSFET and coupled to the first end of the resistor, a drain terminal and a gate terminal coupled to the gate terminal of the first N-channel MOSFET and to the second end of the resistor.

19. A circuit according to claim 13 wherein the transistor is a first transistor, further comprising:

a second transistor having a current path coupled between the first transistor control terminal and the minus terminal.

20. A circuit according to claim 19 wherein:

the first transistor is a bipolar PNP transistor having an emitter coupled to the plus terminal, a collector coupled to the power switch control terminal and a base; and

the second transistor is a bipolar NPN transistor having a collector coupled to the first transistor base, an emitter coupled to the minus terminal and a base coupled to a ground reference.

21. A circuit according to claim 19 wherein:

the first transistor is a high voltage transistor.

22. A circuit according to claim 19 further comprising:

a switch alternatively disconnecting and connecting the control terminal of the first transistor and the current path of the second transistor to the plus terminal.

23. A circuit according to claim 19 further comprising:

a diode coupled in the current path between the first transistor control terminal and the second transistor.

24. A circuit according to claim 19 wherein:

the first transistor is a bipolar PNP transistor having an emitter coupled to the plus terminal, a collector coupled to the source of the PMOS FET and a base; and

the second transistor is a bipolar NPN transistor having a collector coupled to the first transistor base, an emitter coupled to the minus terminal and a base coupled to a ground reference.

25. A circuit according to claim 24 further comprising:

a switch alternatively disconnecting and connecting the control terminal of the first transistor and the current path of the second transistor to the plus terminal.

26. A circuit according to claim 25 wherein the switch is a first switch, further comprising:

a second switch alternatively disconnecting and connecting the emitter of the second transistor to the controller.

27. A circuit according to claim 13 further comprising:

a comparator having a first input terminal coupled to the control terminal of the transistor and a second input terminal coupled to the ground reference.

28. A battery pack for charging a deeply discharged battery cell comprising:

a power switch coupled to the cell and having a control terminal;

plus and minus battery pack terminals for coupling across the series-connected power switch and cell and for coupling to a charger or a load;

a transistor having a current path coupled between the plus terminal and the power switch control terminal and having a control terminal coupled to the minus terminal;

a resistor coupled between the transistor control terminal and the minus terminal; and

a controller having a control terminal coupled to the power switch control terminal.

29. A battery pack according to claim 28 wherein the battery cell is one cell of a plurality of cells connected in series.

30. A battery pack according to claim 28 wherein the battery cell is one cell of a plurality of cells connected in parallel.

31. A battery pack according to claim 28 wherein the power switch further comprises:

a power FET having a drain for coupling to the cell in series, a source and a gate; and

a resistor coupled between the power FET source and gate.

32. A battery pack according to claim 28 wherein the power switch further comprises:

a first and a second power FET coupled back-to-back in series at a common drain node;

a first resistor coupled between the source and gate of the first power FET; and

a second resistor coupled between the source and gate of the second power FET.

33. A battery pack according to claim 28 wherein the power switch further comprises:

two power FETs coupled back-to-back in series at a common source node and a common gate node, the common gate node being the control terminal; and

a resistor coupled between the common source node and the common gate node.

34. A battery pack according to claim 33 wherein the controller further comprises:

a high voltage transistor coupled to the power switch control terminal; and

a switch coupling the plus terminal to the high voltage transistor.

35. A battery pack according to claim 28 wherein the transistor is a first transistor, further comprising:

a second transistor having a current path coupled between the first transistor control terminal and the minus terminal.

36. A battery pack according to claim 35 wherein:

the first transistor is a bipolar PNP transistor having an emitter coupled to the plus terminal, a collector coupled to the power switch control terminal and a base; and

the second transistor is a bipolar NPN transistor having a collector coupled to the first transistor base, an emitter coupled to the minus terminal and a base coupled to a ground reference.

37. A battery pack according to claim 35 wherein:

the first transistor is a high voltage transistor.

38. A battery pack according to claim 35 further comprising:

a switch alternatively disconnecting and connecting the control terminal of the first transistor and the current path of the second transistor to the plus terminal.

39. A battery pack according to claim 35 further comprising:

a diode coupled in the current path between the first transistor control terminal and the second transistor.

40. A battery pack according to claim 35 wherein:

the first transistor is a bipolar PNP transistor having an emitter coupled to the plus terminal, a collector coupled to the source of the PMOS FET and a base; and

the second transistor is a bipolar NPN transistor having a collector coupled to the first transistor base, an emitter coupled to the minus terminal and a base coupled to a ground reference.

41. A battery pack according to claim 40 further comprising:

a switch alternatively disconnecting and connecting the control terminal of the first transistor and the current path of the second transistor to the plus terminal.

42. A battery pack according to claim 41 wherein the switch is a first switch, further comprising:

a second switch alternatively disconnecting and connecting the emitter of the second transistor to a gate terminal of the controller high voltage transistor.

43. A battery pack according to claim 34 wherein the high voltage transistor comprises:

a PMOS FET having a source coupled to the plus terminal, a drain coupled to the two power FETs at the common gate node and a gate coupled to a node between the power switch and the cell.

44. A battery pack according to claim 33 wherein the two power FETs include:

a first N-channel MOSFET having a source terminal coupled to a first end of the resistor, a drain terminal and a gate terminal coupled to the second end of the resistor; and

a second N-channel MOSFET having a source terminal coupled to the source terminal of the first N-channel MOSFET and coupled to the first end of the resistor, a drain terminal and a gate terminal coupled to the gate terminal of the first N-channel MOSFET and to the second end of the resistor.

45. A battery pack according to claim 28 further comprising:

a comparator having a first input terminal coupled to the control terminal and a second input terminal coupled to the ground reference.