Two-dimensional inverse discrete cosine transform processor

• US 5,636,152 A
• Filed: 04/28/1995
• Issued: 06/03/1997
• Est. Priority Date: 04/28/1995
• Status: Expired due to Term

• Current Assignee: National Cheng KUNG University (Government of The Republic of China)
• Original Assignee: National Cheng KUNG University (Government of The Republic of China), United Microelectronics Corporation
• Inventors: Yang, Jar-Ferr, Hisa, Shih-Chang, Hwang, Chyou-Hsiung, Chen, Zhi-Hsien
• Primary Examiner(s): Mai, Tan V.
• Assistant Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US08/431,268
• Time in Patent Office: 767 Days
• Field of Search: 364/725, 364/726, 364/727, 364/736, 364/754, 375/240, 381/29, 381/34, 382/232, 382/248
• US Class Current: 708/401
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence

Abstract

A two-dimensional inverse discrete cosine transform (2-D IDCT) processor comprises cosine angle index generators, pipelined multipliers and a symmetrical kernel. The 2-D IDCT processor of the invention has a five-stage pipelined structure for carrying out a coefficient-by-coefficient 2-D IDCT algorithm and can be operated at a clock rate of more than 50 MHz to achieve a pixel rate of about 400 MHz.

Claims

1. A data processor which carries out a two-dimensional inverse discrete cosine transform (IDCT) for transforming data representing an N×

N matrix into N×

N transformed data, said processor comprising;

a pipelined multiplier for multiplying a non-zero input coefficient of said N×

N matrix with ROM data determined by coordinate parameters of said input coefficient;

a cosine angle index generator for generating a positive angle index and a negative angle index from said coordinate parameters;

a mapping module receiving said positive angle index and said negative angle index for generating one-coefficient-only results based on said positive and negative angle indices and output data from the pipelined multiplier;

##EQU29## adders for summing said one-coefficient-only results;

an accumulator for accumulating data from said adders and generating said N×

N transformed data.

2. A data processor according to claim 1 having a five-stage pipelined structure which comprises an input buffer stage, two cosine angle index and pipelined multiplier stages, a mapping adder stage and an accumulator stage.

3. A data processor according to claim 1, wherein said pipelined multiplier has a hierarchical structure thereby reducing the dimension of each of said multipliers with respect to the dimension that would be necessary without a hierarchical structure.

4. A data processor according to claim 3, wherein said pipelined multiplier has a 3-stage hierarchical structure whose cell multiplier has a dimension of ##EQU30##

5. A data processor according to claim 1, wherein said cosine angle index generator comprises a positive angle index generator and a negative cosine angle index generator.

6. A data processor according to claim 5, wherein said cosine angle indices comprise a signed bit and are simplified.

7. A data processor according to claim 5, wherein said negative cosine angle index generator comprises means for generating, by cross mapping, negative cosine angle indices from positive cosine angle indices produced by said positive cosine angle index generator.

8. A data processor according to claim 1, wherein said accumulator kernel module comprises a first-type sub-module and three second-type sub-modules.

9. A data processor according to claim 8, wherein said first-type sub-module comprises an adder and a latch.

10. A data processor according to claim 8, wherein said second-type sub-module comprises a sign change unit, an adder and a latch.

11. A data processor according to claim 1 wherein said accumulator comprises a symmetrical kernel module array.

12. A data processor according to claim 1 further comprising a plurality of output buffers.

13. A data processor according to claim 12, wherein said output buffers comprise shift registers.

14. A data processor according to claim 1, further comprising means for obtaining said non-zero input coefficient from a variable-length coding unit.

15. A data processor according to claim 1, further comprising means for obtaining said coordinate parameters from run length values.

16. A data processor according to claim 12 further comprising a plurality of post adders connecting to said output buffers.