Power supply including a detection and switch system for uni-plane and split-plane devices

• US 5,637,991 A
• Filed: 04/21/1995
• Issued: 06/10/1997
• Est. Priority Date: 04/21/1995
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Mallory, Joseph D., Titus, Joshua, Vivio, Joseph A., Brown, Alan E.
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US08/426,390
• Time in Patent Office: 781 Days
• Field of Search: 323/269, 323/272, 323/282, 323/285, 363/78, 363/142
• US Class Current: 323/282
• CPC Class Codes: G05F 1/44 semiconductor devices only
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A power supply including a detection and switch system for sensing either a uni-plane or a split-plane device connected to a socket and for providing one or two supply voltages, respectively. In one embodiment, a dual output regulator includes first and second regulators with corresponding first and second feedback circuits and comparators for regulating first and second outputs, respectively. A switch circuit connects the second feedback circuit to the comparator of the second regulator in split-plane mode for providing the second output. However, the switch circuit connects the first feedback circuit to the comparator of the second regulator in uni-plane mode where the two outputs are coupled together by a uni-plane device, so that the two outputs are regulated at the same level. A detection circuit monitors the output signals and controls the switch circuit depending upon whether a uni-plane or split-plane device is detected. The detection circuit includes a comparator which compares the output voltages, which are the same if connected to a uni-plane device or separated by a predetermined amount if connected to a split-plane device. In one regulator embodiment, the outputs are compared after reaching regulation and in a second regulator embodiment, one regulator is momentarily disabled for making the comparison while either one or both outputs voltages are increasing. In another embodiment, two separate power supplies are included for providing separate voltage levels if a split-plane device is connected, where the second power supply is disconnected if a uni-plane device is connected.

Claims

1. A detection and switch system for a power supply which provides power to a device, the power supply including two voltage supplies and corresponding outputs for providing one output voltage in a uni-plane mode if the device is a uni-plane device and for providing two separate output voltages in a split-plane mode if the device is a split-plane device, said detection and switch system comprising:

a switch circuit for coupling to the two voltage supplies and receiving a select signal for selecting between uni-plane and split-plane modes; and

a detection circuit for monitoring at least one of the outputs of the two voltage supplies and for providing said select signal to said switching circuit for selecting the appropriate mode based on the voltage level of at least one of the output voltages.

2. The detection and switch system of claim 1, wherein said switch circuit initially selects the split-plane mode upon power-up.

3. The detection and switch system of claim 1, wherein said detection circuit compares the output voltages of the two voltage supplies and asserts said select signal based on the voltage difference between the outputs.

4. The detection and switch system of claim 1, wherein the two voltage supplies include first and second voltage regulators including separate feedback circuits providing first and second corresponding feedback signals for regulating first and second output voltage levels, respectively, and wherein the second voltage regulator includes an error amplifier for comparing one of the first and second feedback signals with a reference voltage for regulating the second output voltage.

5. The detection and switch system of claim 4, wherein said switch circuit comprises:

a first analog gate receiving the first feedback signal for providing the first feedback signal to the error amplifier of the second voltage regulator when activated; and

a second analog gate receiving the second feedback signal for providing the second feedback signal to the error amplifier of the second voltage regulator when activated.

6. The detection and switch system of claim 5, wherein said detection circuit comprises:

a latch circuit for providing a first enable signal to said first analog gate and a second enable signal to said second analog gate for enabling only one of said first and second analog gates at a time;

a timing circuit coupled to said latch circuit for setting said latch circuit upon power-up to initially select said second analog gate, said timing circuit receiving a reset signal and establishing a predetermined time period from power-up, wherein if said reset signal is asserted within said predetermined time period, said timing circuit toggles said latch circuit to enable said first analog gate for selecting the uni-plane mode; and

a comparator circuit for comparing the first and second output voltage levels and asserting said reset signal if the difference between the voltage levels of the first and second output voltages is less than a predetermined amount.

7. The detection and switch system of claim 6, wherein said detection circuit includes:

said latch circuit comprising a latch having a set and a reset input; and

said timing circuit comprising;

a first timer for providing a set signal for a first predetermined time period after power-up to said set input of said latch for initially selecting the split-plane mode;

a second timer for providing a reset enable signal for a second predetermined time period after power-up, said second predetermined time period being longer than said first predetermined time period, wherein said second timer negates said reset enable signal after said second predetermined time period has expired; and

a gate receiving said set signal to negate said reset input of said latch during said first predetermined time period, said gate further receiving said reset enable signal and said reset signal for resetting said latch to switch to the uni-plane mode if said reset signal is asserted before said second predetermined time period has expired.

8. The detection and switch system of claim 7, wherein both said first and second time periods expire after the first and second output voltages reach a regulating level.

9. The detection and switch system of claim 6, wherein said detection circuit includes:

said latch circuit comprising a latch having a set and a reset input; and

said timing circuit comprising;

a first timer for providing a set signal for a first predetermined time period after power-up to said set input of said latch for initially selecting the split-plane mode;

a second timer receiving said set signal for providing a reset enable signal for a second predetermined time period initiated upon the expiration of said first predetermined time period when said set signal is negated; and

a gate receiving said set signal to negate said reset input of said latch during said first predetermined time period, said gate further receiving said reset enable signal and said reset signal for resetting said latch to select the uni-plane mode if said reset signal is asserted during said second predetermined time period.

10. The detection and switch system of claim 9, wherein said first and second predetermined time periods both expire after the first and second output voltages reach a regulating level.

11. The detection and switch system of claim 5, further comprising:

a disable circuit for disabling the second voltage regulator upon power-up to when the first output voltage is greater than a first reference voltage;

a latch circuit for providing a first enable signal to said first analog gate and a second enable signal to said second analog gate for enabling only one of said first and second analog gates at a time;

a first comparator for asserting a set signal to said latch circuit to select the split-plane mode upon power-up and until the first output voltage is greater than a second reference voltage, wherein said second reference voltage is less than said first reference voltage;

a second comparator for asserting said reset signal if the first output voltage is greater than said second output voltage;

a timing circuit receiving said set signal and for providing a reset enable signal for a predetermined time period initiated after said set signal is negated; and

a gate receiving said reset enable signal and said reset signal for resetting said latch circuit to select the uni-plane mode if said reset signal is asserted during said predetermined time period.

12. The detection and switch system of claim 11, wherein said first and second reference voltages are both below final regulating levels of the first and second output voltages, so that the mode is selected prior to the first and second output voltages reaching regulating voltage levels.

13. The detection and switch system of claim 1, wherein the two voltage supplies include a first power supply providing a first output voltage and a second power supply providing a second output voltage.

14. The detection and switch system of claim 13, wherein said switch circuit couples the second power supply to provide the second output voltage to the device in split-plane mode and disconnects the second power supply in uni-plane mode.

15. The detection and switch system of claim 14, wherein said switch circuit includes a field effect transistor for coupling or disconnecting the second power supply.

16. The detection and switch system of claim 13, wherein said detection circuit comprises:

means for generating a reference signal; and

a comparator for comparing a supply voltage developed by the device in response to receiving the first output voltage with said reference signal.

17. The detection and switch system of claim 16, wherein said comparator asserts said select signal to indicate split-plane mode while said supply voltage is less than said reference signal.

18. The detection and switch system of claim 17, wherein said switch circuit comprises:

a latch receiving said select signal;

a supervisory circuit for asserting a power good signal when a primary voltage source achieves a regulating voltage level, said power good signal clocking said latch when asserted;

a gate coupled to said latch and receiving said power good signal, said gate having an output indicating split-plane mode and switching based on the state of said latch when clocked; and

a switch coupled to said gate for connecting and disconnecting the second power supply to the device.

19. The detection and switch system of claim 18, wherein the first power supply is programmable and coupled to said latch, wherein the first power supply asserts the first output voltage at one voltage level in split-plane mode and at a second voltage level in uni-plane mode.

20. A dual output power supply for providing source voltage to either a uni-plane or a split-plane device, comprising:

a first voltage regulator including a first feedback circuit for regulating a first output voltage;

a second voltage regulator including a second feedback circuit for regulating a second output voltage according to a split-plane mode; and

a switch circuit for disconnecting said second feedback circuit from, while coupling said first feedback circuit to, said second voltage regulator according to a uni-plane mode wherein said first and second output voltages are regulated at the same voltage level.

21. The power supply of claim 20, wherein said switch circuit comprises:

a first switch for coupling said first feedback circuit to said second voltage regulator according to said uni-plane mode; and

a second switch for coupling said second feedback circuit to said second voltage regulator according to said split-plane mode.

22. The power supply of claim 21, further comprising:

said first switch including an analog gate receiving a first enable signal;

said second switch including an analog gate receiving a second enable signal;

a latch circuit for providing said first and second enable signals for activating only one of said first and second analog gates at a time; and

a detection circuit coupled to said latch circuit for initializing said latch circuit according to said split-plane mode upon power-up and for switching said latch circuit according to said uni-plane mode if said first and second output voltages differ by less than a predetermined amount after power-up.

23. The power supply of claim 20, further comprising:

a detection circuit coupled to said switch circuit for initializing said switch circuit according to said split-plane mode upon power-up and for toggling said switch circuit according to said uni-plane mode if said first and second output voltages are at different voltage levels after power-up.

24. The power supply of claim 23, wherein said detection circuit comprises:

a disable circuit for disabling said second voltage regulator from regulating said second output voltage until said first output voltage reaches a predetermined voltage level;

said switch circuit initialized according to said split-plane mode upon power-up; and

a comparator for toggling said switch circuit according to said uni-plane mode if the difference between said first and second output voltages is greater than a predetermined amount before said first output voltage reaches said predetermined voltage level.

25. The power supply of claim 24, wherein said predetermined voltage level is substantially less than regulated voltage level of both said first and second output voltages.

26. The power supply of claim 24, further comprising:

said disable circuit including a second comparator for comparing said first output voltage with said predetermined voltage level; and

a third comparator for asserting a set signal to initialize said switch circuit upon power-up until said first output voltage reaches a second predetermined voltage level being less than said predetermined voltage level, wherein said set signal is then negated.

27. The power supply of claim 26, further comprising:

said switch circuit including a latch circuit receiving said set signal for initializing said switch circuit according to said split-plane mode upon power-up, said latch circuit receiving a reset signal for toggling said switch circuit according to said uni-plane mode; and

said comparator asserting a toggle signal if the difference between said first and second output voltages is greater than said predetermined amount; and

a timing circuit for monitoring said toggle signal for a predetermined time period after said set signal is negated, wherein said timing circuit asserts said reset signal if said toggle signal is asserted during said predetermined time period.

28. A system for providing source voltage to a device which is either a uni-plane device or a split-plane device, comprising:

a first power supply providing a first output voltage to the device;

a second power supply providing a second output voltage to the device;

a switch circuit for coupling said second power supply to the device if split-plane and for disconnecting said second power supply if uni-plane; and

a comparator circuit coupled to said first power supply and said switch circuit for controlling said switch circuit based on the voltage level of the device.

29. The system of claim 28, the device including a first portion receiving said first output voltage and a second portion receiving said second output voltage, further comprising:

means for providing a reference signal; and

said comparator circuit comparing the voltage of the first portion of the device with said reference signal for asserting a signal indicative of the type of device.

30. The system of claim 29, wherein said switch circuit comprises:

a latch circuit receiving said signal indicative of the type of device;

a supervisory circuit for asserting a power good signal to said latch circuit, said power good signal initially being de-asserted to control said switch circuit to select split-plane and then clocking said latch circuit when asserted; and

a transistor circuit coupled to said latch circuit.