Linear list based DMA control structure

• US 5,644,784 A
• Filed: 03/03/1995
• Issued: 07/01/1997
• Est. Priority Date: 03/03/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Peek, Gregory A.
• Primary Examiner(s): Auve, Glenn A.
• Application Number:
  US08/398,439
• Time in Patent Office: 851 Days
• Field of Search: 395/842, 395/844, 395/853, 395/854, 395/855, 395/843, 395/846
• US Class Current: 710/24
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Linear list based direct memory access (DMA) control structure for controlling a DMA processor through a linear list of DMA descriptors in memory. A descriptor entry is deposited at the end of the linear list. Each descriptor entry has an address associated with their location in the linear list. A pointer to the linear list points to a single location in the linear Fist. A next descriptor entry is accessed by decrementing the address corresponding to the single location. The descriptor entries are read from the linear list of DMA descriptors DMA transfers are performed.

Claims

1. A method for controlling a DMA controller through a linear list of DMA descriptors in memory, said method comprising the steps of:

writing descriptor entries in said linear list of DMA descriptors, each said descriptor entry being added at the end of said linear list in said memory; and

reading said descriptor entry from said linear list of DMA descriptors starting at an address pointed to by a descriptor list pointer, said reading being performed by the DMA controller, each descriptor entry being accessed by the DMA controller in the order said descriptor entries were written to said linear list.

2. The method of claim 1 wherein said step of reading further comprises the step of reading a descriptor control word associated with said descriptor entry.

3. The method of claim 1 further comprising the steps of:

reading a wrap bit; and

reading a new descriptor list pointer value from a descriptor list base pointer if said wrap bit is set to true.

4. The method of claim 3 further comprising the steps of:

reading a valid bit associated with said descriptor entry; and

reading a source address, a destination address and a length of data to be transferred associated with said descriptor entry if said valid bit is set to true.

5. The method of claim 4 further comprising the step of performing a DMA transfer.

6. An apparatus for controlling a DMA controller through a linear list of DMA descriptors in memory, said apparatus comprising:

a linear list of descriptor entries having a descriptor list pointer pointing to an address corresponding to one of said descriptor entries;

a CPU writing said descriptor entries in said linear list; and

a DMA controller reading said descriptor entries from said linear list, each said descriptor entry being accessed by said DMA controller in the order said descriptor entries were written to said linear list.

7. The apparatus of claim 6 wherein said descriptor entries comprises:

a control word;

a source address from which data is to be transferred; and

a destination address where said data is to be transferred.

8. The apparatus of claim 7 further comprising:

a valid bit to indicate whether said descriptor entries are valid;

a wrap bit to indicate whether there is a new beginning of said linear list; and

a length of said data to be transferred.

9. The apparatus of claim 6 wherein said DMA controller further comprises:

a descriptor list pointer pointing to an address in said linear list;

a comparator coupled to said descriptor list pointer, said comparator for monitoring new entries in said linear list;

a multiplexer coupled to said descriptor list pointer;

a length counter for holding length loaded from said descriptor entries;

a source address counter for holding source address loaded from said descriptor entries; and

a destination address counter for holding destination address loaded from said descriptor entries.

10. An apparatus for controlling a DMA controller through a linear list of DMA descriptors in memory, said apparatus comprising:

means for storing a linear list of descriptor entries having a descriptor list pointer pointing to an address corresponding to one of said descriptor entries;

means for writing said descriptor entries in said linear list; and

means for reading said descriptor entries from said linear list, each said descriptor entry being accessed by said DMA controller in the or linear list.

11. The apparatus of claim 10 wherein said descriptor entries comprises:

means for storing a control word;

means for storing a source address from which data is to be transferred; and

means for storing a destination address where said data is to be transferred.

12. The apparatus of claim 11 further comprising:

means for indicating whether said descriptor entries are valid;

means for indicating whether there is a new beginning of said linear list; and

means for storing a length of said data to be transferred.

13. The apparatus of claim 10 wherein said DMA controller further comprises:

means for pointing to an address in said linear list;

means for monitoring new entries in said linear list;

means for multiplexing coupled to said descriptor list pointer;

means for holding length loaded from said descriptor entries;

means for holding source address loaded from said descriptor

entries; and

means for holding destination address loaded from said descriptor entries.

14. A system for controlling a DMA controller through a linear list of DMA descriptors in memory, said system comprising:

a linear list of descriptor entries having a descriptor list pointer pointing to an address corresponding to one of said descriptor entries;

a CPU writing said descriptor entries in said linear list; and

a DMA controller reading said descriptor entries from said linear list, each said descriptor entry being accessed by said DMA controller in the order said descriptor entries were written to said linear list.

15. The system of claim 14 wherein said descriptor entries comprises:

a control word;

a source address from which data is to be transferred; and

a destination address where said data is to be transferred.

16. The system of claim 15 further comprising:

a valid bit to indicate whether said descriptor entries are valid;

a wrap bit to indicate whether there is a new beginning of said linear list; and

a length of said data to be transferred.

17. The system of claim 14 wherein said DMA controller further comprises:

a descriptor list pointer pointing to an address in said linear list;

a comparator coupled to said descriptor list pointer, said comparator for monitoring new entries in said linear list;

a multiplexer coupled to said descriptor list pointer;

a length counter for holding length loaded from said descriptor entries;

a source address counter for holding source address loaded from said descriptor entries; and

a destination address counter for holding destination address loaded from said descriptor entries.

18. A system for controlling a DMA controller through a linear list of DMA descriptors in memory, said system comprising:

means for storing a linear list of descriptor entries having a descriptor list pointer pointing to an address corresponding to one of said descriptor entries;

means for writing said descriptor entries in said linear list; and

means for reading said descriptor entries from said linear list, each said descriptor entry being accessed by said DMA controller in the order said descriptor entries were written to said linear list.

19. The system of claim 18 wherein said descriptor entries comprises:

means for storing a control word;

means for storing a source address from which data is to be transferred; and

means for storing a destination address where said data is to be transferred.

20. The system of claim 19 further comprising:

means for indicating whether said descriptor are valid;

means for indicating whether there is a new beginning of said linear list; and

means for indicating a length of said data to be transferred.

21. The system of claim 18 wherein said DMA controller further comprises:

means for pointing to an address in said linear list;

means for monitoring new entries in said linear list;

means for multiplexing coupled to said descriptor list pointer;

means for holding length loaded from said descriptor entries;

means for holding source address loaded from said descriptor entries; and

means for holding destination address loaded from said descriptor entries.