Method of bonding wafers having vias including conductive material

• US 5,646,067 A
• Filed: 06/05/1995
• Issued: 07/08/1997
• Est. Priority Date: 06/05/1995
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Gaul, Stephen Joseph
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): BILODEAU, THOMA
• Application Number:
  US08/461,951
• Time in Patent Office: 764 Days
• Field of Search: 437/67, 437/78, 437/180, 437/190, 437/192, 437/193, 437/203, 437/915, 437/974, 437/228, 148/DIG. 12, 148/DIG. 135
• US Class Current: 438/458
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16105 the bump connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/16108 the bump connector not being orthogonal to the surface
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/012 : Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10S 148/135 : Removal of substrate

Abstract

A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. The via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies with vias can be stacked on top of each other or surface mounted to printed circuit boards or other substrate.

Claims

1. A method for fabricating surface mountable integrated circuits comprising the steps of:

providing a device wafer of monocrystalline silicon material with first and second surfaces and with integrated circuits formed on the first surface of said device wafer;

forming an oxide layer between the second surface of the device wafer and a handle wafer, said oxide layer bonding the handle wafer to the device wafer for supporting the device wafer;

forming a via in the device wafer, said via comprising a first open end on the first surface of the device wafer, an elongated passage extending from said open end a controlled depth into the handle wafer and terminating at a second end closed by said handle wafer;

depositing a conductive material in the via over the elongated surface and the closed end of the via;

removing the handle wafer to expose the conductive material coated on the via surface.

2. The method of claim 1 wherein the handle wafer is removed to expose a surface of said oxide bonding layer and the conductive material of the second end of the via extends beyond the surface of the oxide bonding layer.

3. The method of claim 1 wherein the conductive material deposited over the surface of the via comprises a metal deposited on the via surface.

4. The method of claim 3 wherein the metal comprises a first layer of a barrier metal and a second layer of an adhesion metal deposited on the barrier metal.

5. The method of claim 4 wherein the barrier metal is one metal selected from the group consisting of titanium nitride, copper, lead, platinum, and nickel and the adhesion metal is another metal selected from the group consisting of titanium nitride, chromium, titanium, and titanium tungsten.

6. The method of claim 4 further comprising the step of filling the via with polysilicon.

7. The method of claim 6 further comprising the step of planarizing the layers of adhesion metal, barrier metal and polysilicon.

8. The method of claim 1 wherein the step of depositing a conductive material comprises the steps of depositing a layer of titanium nitride, depositing a layer of tungsten on the layer of titanium nitride, and depositing a layer of polysilicon over the titanium nitride to fill the via, and planarizing the layers of titanium nitride, tungsten, and polysilicon.

9. The method of claim 1 further comprising the step of dielectrically isolating the surface of the via from the monocrystalline silicon material before depositing the conductive material.

10. The method of claim 9 further comprising the step of depositing a dielectric material on the surface of the via.

11. The method of claim 10 wherein the deposited dielectric is one selected from the group consisting of silicon dioxide, silicon nitride, and diamond.

12. The method of claim 9 further comprising the step of forming a dielectric layer on the surface of the via.

13. The method of claim 12 wherein the monocrystalline silicon material in the via is oxidized to form a dielectric layer on the surface of the via.

14. The method of claim 1 wherein the via is filled to the first surface with a conductive material.

15. The method of claim 1 comprising the further steps of:

filling the via with photoresist;

developing a portion of the photoresist extending a controlled depth from the first surface of the wafer;

removing the developed portion of resist from the end of the via between the first surface and the controlled depth;

filling the via with a conductive material between the first surface and the controlled depth.

16. The method of claim 1 comprising the further steps of:

depositing a metal contact layer on the surface of the wafer;

patterning the metal contact layer to provide conductive paths between the integrated circuit and the vias.

17. The method of claim 1 wherein the exposed conductive material of the via is silicided.